Datasheet

DS2148/DS21Q48
7 of 73
Figure 1-1. DS2148 Block Diagram
V
D
D
V
S
S
P
o
w
e
r
C
o
n
n
e
c
t
i
o
n
s
2
2
V
C
O
/
P
L
L
M
C
L
K
2.048MHz to
1.544MHz PLL
Jitter
Attenuator
MUX
VSM
A
n
a
l
o
g
L
o
o
p
b
a
c
k
L
i
n
e
D
r
i
v
e
r
s
C
S
U
F
i
l
t
e
r
s
W
a
v
e
S
h
a
p
i
n
g
L
o
c
a
l
L
o
o
p
b
a
c
k
T
R
I
N
G
T
T
I
P
J
i
t
t
e
r
A
t
t
e
n
u
a
t
i
o
n
(
c
a
n
b
e
p
l
a
c
e
d
i
n
e
i
t
h
e
r
t
r
a
n
s
m
i
t
o
r
r
e
c
e
i
v
e
p
a
t
h
)
F
i
l
t
e
r
P
e
a
k
D
e
t
e
c
t
C
l
o
c
k
/
D
a
t
a
R
e
c
o
v
e
r
y
R
R
I
N
G
R
T
I
P
Optional Termination
Remote Loopback (Dual Mode)
Unframed
All Ones
Insertion
D
0
t
o
D
7
/
A
D
0
t
o
A
D
7
P
B
T
S
W
R
*
(
R
/
W
*
)
R
D
*
(
D
S
*
)
A
L
E
(
A
S
)
A
0
t
o
A
4
8
5
S
D
O
S
D
I
S
C
L
K
I
N
T
*
C
S
*
2
1
B
I
S
0
B
I
S
1
C
o
n
t
r
o
l
a
n
d
T
e
s
t
P
o
r
t
(
r
o
u
t
e
d
t
o
a
l
l
b
l
o
c
k
s
)
M
U
X
(
t
h
e
S
e
r
i
a
l
,
P
a
r
a
l
l
e
l
,
a
n
d
H
a
r
d
w
a
r
e
I
n
t
e
r
f
a
c
e
s
s
h
a
r
e
d
e
v
i
c
e
p
i
n
s
)
HRST*
TEST
16.384MHz or
8.192MHz or
4.096MHz or
2.048MHz
Synthesizer
BPCLK
RPOS
RCLK
RNEG
TPOS
TCLK
TNEG
JACLK
MUX
See Figure 3-2
See Figure 3-3
PBEO
H
a
r
d
w
a
r
e
I
n
t
e
r
f
a
c
e
C
o
n
t
r
o
l
a
n
d
I
n
t
e
r
r
u
p
t
P
a
r
a
l
l
e
l
I
n
t
e
r
f
a
c
e
S
e
r
i
a
l
I
n
t
e
r
f
a
c
e
R
e
m
o
t
e
L
o
o
p
b
a
c
k
MUX RCL/LOTC