Datasheet

DS2148/DS21Q48

16 of 73

NAME PIN I/O FUNCTION

SDI 6 I

Serial Data Input. Sampled on rising edge (ICES = 0) or the falling edge

(ICES = 1) of SCLK.

SDO 7 O

Serial Data Output. Valid on the falling edge (OCES = 0) or the rising

edge (OCES = 1) of SCLK.

TCLK 43 I

Transmit Clock. A 2.048 MHz or 1.544 MHz primary clock. Used to

clock data through the transmit side formatter. Can be sourced internally

by MCLK or RCLK. See Common Control Register 1 and Figure 1-3

TEST 26 I

Tri-State Control. Set high to tri-state all outputs and I/O pins (including

the parallel control port). Set low for normal operation. Useful in board

level testing.

TNEG 42 I

Transmit Negative Data. Sampled on the falling edge (CCR2.1 = 0) or

the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted out onto

the line.

TPOS 41 I

Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0) or the

rising edge (CCR2.1 = 1) of TCLK for data to be transmitted out onto the

line.

TTIP/TRING 34/37 O

Transmit Tip and Ring . Analog line driver outputs. These pins connect

via a step-up transformer to the line. See Section 5

for details.

21/36 -

5.0V ±5% Positive Supply

VSM 20 I Voltage Supply Mode. Should be tied high for 5V operation.

22/35 -

Signal Ground