Datasheet

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
123 of 124
Figure 20-12. Transmit System Side AC Timing
Figure 20-13. Transmit Line Interface Side AC Timing
t
F
t
R
TSYSCLK
TSER
TCHCLK / CO
t
t
SL
t
SH
SP
TSSYNC
TCHBLK
t
D3
t
D3
t
t
t
SU
HD
SU
t
HD
Notes:
1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
2. TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic store is enabled.
CI
t
SC
t
WC
TCLKO
TPOSO, TNEGO
t
DD
t
F
t
R
TCLKI
TPOSI, TNEGI
t
t
LL
t
LH
LP
t
HD
t
SU