Datasheet

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
118 of 124
Figure 20-8. Receive-Side AC Timing
t
D1
1
t
D2
t
D2
t
D2
t
D2
RSER / RDATA / RSIG
RCHCLK
RCHBLK
RSYNC
RLCLK
RLINK
t
D1
Notes:
1. RSYNC is in the output mode (RCR1.5 = 0).
2. RLCLK will only pulse high during Sa bit locations as defined in RCR2; no relationship
between RLCLK and RSYNC or RFSYNC is implied.
RCLK
t
D2
RFSYNC / RMSYNC
MSB of
Channel 1
2
Sa4 to Sa8
Bit Position