Datasheet

DS21352/DS21552
135 of 137
Figure 24-11 TRANSMIT SIDE TIMING
t
F
t
R
1
TCLK
TSER / TSIG /
TDATA
TCHCLK
t
t
CL
t
CH
CP
TSYNC
TSYNC
TLINK
TLCLK
TCHBLK
t
D2
t
D2
t
D2
t
t
t
t
t
t
HD
SU
D2
SU
HD
D1
t
HD
2
Notes:
1. TSYNC is in the output mode (TCR2.2 = 1).
2. TSYNC is in the input mode (TCR2.2 = 0).
3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled.
4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled.
5. TLINK is only sampled during F-bit locations.
6. No relationship between TCHCLK and TCHBLK and the other signals is implied.
5
TESO
t
SU