Datasheet

DS21352/DS21552
128 of 137
Figure 24-4 INTEL BUS READ TIMING (BTS=0 / MUX=0)
Figure 24-5 INTEL BUS WRITE TIMING (BTS=0 / MUX=0)
Address Valid
Data Valid
A
0 to A7
D0 to D7
WR*
CS*
RD*
0ns min.
0ns min.
75ns max.
0ns min.
5ns min. / 20ns max.
t1
t2 t3 t4
t5
Address Valid
A
0 to A7
D0 to D7
RD*
CS*
WR*
0ns min.
0ns min.
75ns min.
0ns min.
10ns
min.
10ns
min.
t1
t2 t6 t4
t7 t8