Datasheet

DS21352/DS21552
80 of 137
TDC2: TRANSMIT HDLC DS0 CONTROL REGISTER 2 (Address=93 Hex)
(MSB) (LSB)
TDB8 TDB7 TDB6 TDB5 TDB4 TDB3 TDB2 TDB1
SYMBOL POSITION NAME AND DESCRIPTION
TDB8 TDC2.7 DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to stop this bit from
being used.
TDB7 TDC2.6 DS0 Bit 7 Suppress Enable. Set to one to stop this bit from being used.
TDB6 TDC2.5 DS0 Bit 6 Suppress Enable. Set to one to stop this bit from being used.
TDB5 TDC2.4 DS0 Bit 5 Suppress Enable. Set to one to stop this bit from being used.
TDB4 TDC2.3 DS0 Bit 4 Suppress Enable. Set to one to stop this bit from being used.
TDB3 TDC2.2 DS0 Bit 3 Suppress Enable. Set to one to stop this bit from being used.
TDB2 TDC2.1 DS0 Bit 2 Suppress Enable. Set to one to stop this bit from being used.
TDB1 TDC2.0 DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to stop this bit from
being used.
15.4 LEGACY FDL SUPPORT
15.4.1 OVERVIEW
In order to provide backward compatibility to the older DS2152 device, the DS21352/552 maintains the
circuitry that existed in the previous generation of the T1 Quad Framer. Sections 15.4.2 and 15.4.3 cover
the circuitry and operation of this legacy functionality. In new applications, it is recommended that the
HDLC controller and BOC controller described in Section 15.3 are used. On the receive side, it is
possible to have both the new HDLC/BOC controller and the legacy hardware working at the same time.
On the transmit side the HDLC/BOC controller can be assigned to a DSO while the legacy function
supports the FDL via software. Software for supporting the legacy functions is available from Dallas
Semiconductor.
15.4.2 RECEIVE SECTION
In the receive section, the recovered FDL bits or Fs bits are shifted bit–by–bit into the Receive FDL
register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms (8 times 250 us). The framer
will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via IMR2.4,
the INT pin will toggle low indicating that the buffer has filled and needs to be read. The user has 2 ms to
read this data before it is lost. If the byte in the RFDL matches either of the bytes programmed into the
RFDLM1 or RFDLM2 registers, then the SR2.2 bit will be set to a one and the INT pin will toggled low
if enabled via IMR2.2. This feature allows an external microcontroller to ignore the FDL or Fs pattern
until an important event occurs.