Datasheet

DS21352/DS21552
52 of 137
8.2 PATH CODE VIOLATION COUNT REGISTER (PCVCR)
When the receive side of a framer is set to operate in the ESF framing mode (CCR2.3=1), PCVCR will
automatically be set as a 12–bit counter that will record errors in the CRC6 code words. When set to
operate in the D4 framing mode (CCR2.3=0), PCVCR will automatically count errors in the Ft framing
bit position. Via the RCR2.1 bit, a framer can be programmed to also report errors in the Fs framing bit
position. The PCVCR will be disabled during receive loss of synchronization (RLOS=1) conditions. See
Table 8-2 for a detailed description of exactly what errors the PCVCR counts.
PCVCR1: PATH VIOLATION COUNT REGISTER 1 (Address = 25 Hex)
PCVCR2: PATH VIOLATION COUNT REGISTER 2 (Address = 26 Hex)
(MSB) (LSB)
(note 1) (note 1) (note 1) (note 1) CRC/FB11 CRC/FB10 CRC/FB9 CRC/FB8 PCVCR1
CRC/FB7 CRC/FB6 CRC/FB5 CRC/FB4 CRC/FB3 CRC/FB2 CRC/FB1 CRC/FB0 PCVCR2
SYMBOL POSITION NAME AND DESCRIPTION
CRC/FB11 PCVCR1.3 MSB of the 12–Bit CRC6 Error or Frame Bit Error Count (note #2)
CRC/FB0 PCVCR2.0 LSB of the 12–Bit CRC6 Error or Frame Bit Error Count (note #2)
NOTES:
1. The upper nibble of the counter at address 25 is used by the Multiframes Out of Sync Count Register
2. PCVCR counts either errors in CRC code words (in the ESF framing mode; CCR2.3=1) or errors in the framing bit position
(in the D4 framing mode; CCR2.3=0).
Table 8.2 PATH CODE VIOLATION COUNTING ARRANGEMENTS
FRAMING MODE
(CCR2.3)
COUNT Fs ERRORS
(RCR2.1)
WHAT IS COUNTED
IN THE PCVCRs
D4 no errors in the Ft pattern
D4 yes errors in both the Ft & Fs patterns
ESF don’t care errors in the CRC6 code words