Datasheet

DS21352/DS21552
45 of 137
bits of its limit; useful for debugging jitter attenuation operation.
LORC RIR3.4 Loss of Receive Clock. Set when the RCLKI pin has not transitioned for at least 2 us (4
ms max).
FRCL RIR3.3 Framer Receive Carrier Loss. Set when 192 consecutive zeros have been received at
the RPOSI and RNEGI pins; allowed to be cleared when 14 or more ones out of 112
possible bit positions are received.
–RIR3.2Not Assigned. Could be any value when read.
–RIR3.1Not Assigned. Could be any value when read.
–RIR3.0Not Assigned. Could be any value when read.
Table 7-1 RECEIVE T1 LEVEL INDICATION
RL1 RL0 TYPICAL LEVEL RECEIVED
0 0 +2 dB to –7.5 dB
0 1 –7.5 dB to –15 dB
1 0 –15 dB to –22.5 dB
1 1 less than –22.5 dB