Datasheet

DS21352/DS21552
33 of 137
TCR1: TRANSMIT CONTROL REGISTER 1 (Address=35 Hex)
(MSB) (LSB)
LOTCMC TFPT TCPT TSSE GB7S TFDLS TBL TYEL
SYMBOL POSITION NAME AND DESCRIPTION
LOTCMC TCR1.7 Loss Of Transmit Clock Mux Control. Determines whether the transmit side
formatter should switch to RCLK if the TCLK input should fail to transition.
0 = do not switch to RCLK if TCLK stops
1 = switch to RCLK if TCLK stops
TFPT TCR1.6 Transmit F–Bit Pass Through. (see note below)
0 = F bits sourced internally
1 = F bits sampled at TSER
TCPT TCR1.5 Transmit CRC Pass Through. (see note below)
0 = source CRC6 bits internally
1 = CRC6 bits sampled at TSER during F–bit time
TSSE TCR1.4 Transmit Software Signaling Enable. (see note below)
0 = no signaling is inserted in any channel
1 = signaling is inserted in all channels from the TS1-TS12 registers (the TTR registers
can be used to block insertion on a channel by channel basis)
GB7S TCR1.3 Global Bit 7 Stuffing. (see note below)
0 = allow the TTR registers to determine which channels containing all zeros are to be
Bit 7 stuffed
1 = force Bit 7 stuffing in all zero byte channels regardless of how the TTR registers are
programmed
TFDLS TCR1.2 TFDL Register Select. (see note below)
0 = source FDL or Fs bits from the internal TFDL register (legacy FDL support mode)
1 = source FDL or Fs bits from the internal HDLC/BOC controller or the TLINK pin
TBL TCR1.1 Transmit Blue Alarm. (see note below)
0 = transmit data normally
1 = transmit an unframed all one’s code at TPOSO and TNEGO
TYEL TCR1.0 Transmit Yellow Alarm. (see note below)
0 = do not transmit yellow alarm
1 = transmit yellow alarm
NOTE: For a description of how the bits in TCR1 affect the transmit side formatter, see Figure 22-2