Datasheet

DS21352/DS21552
122 of 137
Figure 22-2 TRANSMIT DATA FLOW
Idle Code / Per
Channel LB
TIR1 to TIR3
Software Signaling
Insertion
TS1 to TS12
Bit 7 Stuffing
One's Density Monitor
F-Bit Mux
CRC Mux
AMI or B8ZS Converter /
Blue Alarm Gen.
Software Signaling Enable (TCR1.4)
TPOS TNEG
Transmit Blue (TCR1.1)
B8ZS Enable (CCR2.6)
TFDL Select (TCR1.2)
TFDL
TLINK
CRC Calculation
Pulse Density Enforcer Enable (CCR3.3)
Pulse Density Violation (RIR2.0)
Frame Mode Select (CCR2.7)
D4 Yellow Alarm Select (TCR2.1)
Transmit Yellow (TCR1.0)
TTR1 to TTR3
Bit 7 Zero Suppression Enable (TCR2.0)
Global Bit 7 Stuffing (TCR1.3)
F-Bit Pass Through (TCR1.6)
Frame Mode Select (CCR2.7)
CRC Pass Through (TCR1.5)
Frame Mode Select (CCR2.7)
= Register
= Device Pin
= Selector
KEY:
D4 Bit 2 Yellow
Alarm Insertion
D4 12th Fs Bit
Yellow Alarm Gen.
Frame Mode Select (CCR2.7)
D4 Yellow Alarm Select (TCR2.1)
Transmit Yellow (TCR1.0)
ESF Yellow Alarm Gen.
(00FF Hex in the FDL)
Frame Mode Select (CCR2.7)
Transmit Yellow (TCR1.0)
10
1
0
10
01
1
0
DS2152 TRANSMIT DATA FLOW Figure 15.11
FPS or Ft Bit Insertion
1
0
FDL HDLC & BOC Controller
HDLC/BOC Enable (TBOC.6)
TIR Function Select (CCR4.0)
TIDR
1
0
RSER
In-Band Loop
Code Generator
Per-Channel Code
Generation
10
IBCC
TCD
TCC1 to TCC3
TC1 to TC24
CCR3.1
(note#1)
NOTES:
1. TCLK should be tied to RCLK and TSYNC should be tied to
RFSYNC for data to be properly sourced from RSER.
10
TCD2
DS0 insertion enable (TDC1.7)
1
0
TDC1.5
TCD1 4:0
TCHBLK
DS0 Monitor
FDL Mux
1
0
0
Source Mux
HDLC
ENGINE
TSER
&
TDATA
TSIG
Hardware
Signaling
Insertion
01
TCBR1/2/3
CCR4.1
CCR4.2