Datasheet

DS21352/DS21552
117 of 137
Figure 21-10 TRANSMIT SIDE BOUNDARY TIMING (with elastic store
disabled)
Notes:
1. TSYNC is in the output mode (TCR2.2 = 1)
2. TSYNC is in the input mode (TCR2.2 = 0)
3. TCHBLK is programmed to block channel 2
4. Shown is TLINK/TLCLK in the ESF framing mode
Figure 21-11 TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING (with elastic
store enabled)
Notes:
1. TCHBLK is programmed to block channel 24 (if the TPCSI bit is set, then the signaling data at TSIG will be ignored during
channel 24).
LSB F MSB LSB MSB LSB MSB
CHANNEL 1 CHANNEL 2
CHANNEL 1 CHANNEL 2
ABC/AD/B ABC/AD/B
TCLK
TSER
TSYNC
TSYNC
TSIG
TCHCLK
TCHBLK
TLCLK
TLINK
D/B
1
2
3
4
DON'T CARE
LSB F MSBLSB MSB
CHANNEL 1CHANNEL 24
A B C/A D/B A B C/A D/B
TSYSCLK
TSER
TSSYNC
TSIG
TCHCLK
TCHBLK
CHANNEL 23
A
CHANNEL 23 CHANNEL 24 CHANNEL 1
1