Datasheet

DS21352/DS21552
113 of 137
Figure 21-6 RECEIVE SIDE INTERLEAVE BUS OPERATION, BYTE MODE
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
3. RSYNC is in the input mode (RCR1.5 = 0)
RSER
1
RSYNC
RSIG
1
RSER
2
RSIG
2
FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2
FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2
FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2
FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2
A
BCD
A
BCD
BIT DETAIL
RSER
LSB
RSYSCLK
RSYNC
3
FRAMER 3, CHANNEL 32
MSB
LSB
FRAMER 0, CHANNEL 1
RSIG
FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1
MSB
LSB
FRAMER 1, CHANNEL 1
FRAMER 1, CHANNEL 1
A
BCD