Datasheet

DS21352/DS21552
107 of 137
20. INTERLEAVED PCM BUS OPERATION
In many architectures, the outputs of individual framers are combined into higher speed serial buses to
simplify transport across the system. The DS21352/552 can be configured to allow data and signaling
buses to be multiplexed into higher speed data and signaling buses eliminating external hardware saving
board space and cost.
The interleaved PCM bus option (IBO) supports two bus speeds. The 4.096 MHz bus speed allows two
SCTs to share a common bus. The 8.192 MHz bus speed allows four SCTs to share a common bus. See
Figure 20-1 for an example of 4 devices sharing a common 8.192MHz PCM bus. Each SCT that shares a
common bus must be configured through software and requires the use of one or two device pins. The
elastic stores of each SCT must be enabled and configured for 2.048 MHz operation. See Figure 21-6
and Figure 21-7.
For all bus configurations, one SCT will be configured as the master device and the remaining SCTs will
be configured as slave devices. In the 4.096 MHz bus configuration there is one master and one slave. In
the 8.192 MHz bus configuration there is one master and three slaves. Refer to the IBO register
description for more detail.
IBO: INTERLEAVE BUS OPERATION REGISTER (Address = 94 Hex)
(MSB) (LSB)
- - - - IBOEN INTSEL MSEL0 MSEL1
SYMBOL POSITION NAME AND DESCRIPTION
-IBO.7Not Assigned. Should be set to 0.
-IBO.6Not Assigned. Should be set to 0.
-IBO.5Not Assigned. Should be set to 0.
-IBO.4Not Assigned. Should be set to 0.
IBOEN IBO.3
Interleave Bus Operation Enable
0 = Interleave Bus Operation disabled.
1 = Interleave Bus Operation enabled.
INTSEL IBO.2
Interleave Type Select
0 = Byte interleave.
1 = Frame interleave.
MSEL0 IBO.1 Master Device Bus Select Bit 0. See Table 20-1.
MSEL1 IBO.0 Master Device Bus Select Bit 1. See Table 20-1.