Datasheet

DS21348/DS21Q348
7 of 76
Figure 1-1. DS21348 Block Diagram
VDD
VSS
Power Connections
2
2
VCO / PLL
MCLK
2.048MHz to
1.544MHz PLL
Jitter
A
ttenuato
r
MUX
VSM
A
nalog Loopback
Line Drivers
CSU Filters
Wave Shaping
Local Loopback
TRING
TTIP
Jitter Attenuation
(can be placed in either transmit or receive path)
Filte
r
Peak Detect
Clock / Data
Recovery
RRING
RTIP
Optional
Termination
Remote Loopback (Dual Mode)
Unframed
A
ll Ones
Insertion
D0 to D7 /
A
D0 to AD7
PBTS
W
R(R/W)
R
D(DS)
A
LE(AS)
A
0 to A4
8
5
SDO
SDI
SCLK
I
NT
C
S
21
BIS0
BIS1
Control and Test Port
(routed to all blocks)
MUX (the Serial, Parallel, and Hardware Interfaces share device pins)
H
RST
TEST
16.384MHz or
8.192MHz or
4.096MHz or
2.048MHz
Synthesizer
BPCLK
RPOS
RCLK
RNEG
TPOS
TCLK
TNEG
JACLK
M
U
X
See Figure 3-2
See Figure 1-3
PBEO
Hardware
Interface
Control and
Interrupt
Parallel Interface
Serial Interface
Remote Loopback
MUX RCL/LOTC
DS21348