Datasheet

DS21348/DS21Q348
35 of 76
CCR6 (05H): COMMON CONTROL REGISTER 6
(MSB) (LSB)
LLB RLB ARLBE ALB RJAB ECRS2 ECRS1 ECRS0
SYMBOL POSITION DESCRIPTION
LLB CCR6.7 Local Loopback. In Local Loopback (LLB), transmit data will be looped back
to the receive path passing through the jitter attenuator if it is enabled. Data in
the transmit path will act as normal. See Figure 1-1
and Section 6.2.2 for
details.
0 = loopback disabled
1 = loopback enabled
RLB CCR6.6 Remote Loopback. In Remote Loopback (RLB), data output from the
clock/data recovery circuitry will be looped back to the transmit path passing
through the jitter attenuator if it is enabled. Data in the receive path will act as
normal while data presented at TPOS and TNEG will be ignored.
See Figure 1-1
and Section 6.2.1 for details.
0 = loopback disabled
1 = loopback enabled
ARLBE CCR6.5 Automatic Remote Loopback Enable and Reset. When this bit is set high,
the device will automatically go into remote loopback when it detects loop up
code programmed into the Receive Loop-Up Code Definition Registers
(RUPCD1 and RUPCD2) for a minimum of 5 seconds and it will also set the
RIR2.1 status bit. Once in a RLB state, it will remain in this state until it has
detected the loop code programmed into the Receive Loop-Down Code
Definition Registers (RDNCD1 and RDNCD2) for a minimum of 5 seconds at
which point it will force the device out of RLB and clear RIR2.1. The
automatic RLB circuitry can be reset by toggling this bit from a 1 to a 0. The
action of the automatic remote loopback circuitry is logically ORed with the
RLB (CCR6.6) control bit (i.e., either one can cause a RLB to occur).
ALB CCR6.4 Analog Loopback. In Analog Loopback (ALB), signals at TTIP and TRING
will be internally connected to RTIP and RRING. The incoming signals, from
the line, at RTIP and RRING will be ignored. The signals at TTIP and TRING
will be transmitted as normal. See Figure 1-1
and Section 6.2.3 for more details.
0 = loopback disabled
1 = loopback enabled
RJAB CCR6.3 RCLK Jitter Attenuator Bypass. This control bit allows the receive recovered
clock and data to bypass the jitter attenuation while still allowing the BPCLK
output to use the jitter attenuator. See Figure 1-1
and Section 7.3 for details.
0 = disabled
1 = enabled
ECRS2 CCR6.2 Error Count Register Select 2. See Section 6.4 for details.
ECRS1 CCR6.1 Error Count Register Select 1. See Section 6.4 for details.
ECRS0 CCR6.0 Error Count Register Select 0. See Section 6.4 for details.