Datasheet

DS21348/DS21Q348
15 of 76
NAME PIN I/O FUNCTION
PBTS 44 I
Parallel Bus Type Select. When using the parallel port (BIS1 = 0),
set high to select Motorola bus timing, set low to select Intel bus
timing. This pin controls the function of the RD (DS), ALE (AS),
and WR (R/W) pins. If PBTS = 1 and BIS1 = 0, then these pins
assume the Motorola function listed in parentheses (). In serial port
mode, this pin should be tied low.
RCLK 40 O
Receive Clock. Buffered recovered clock from the line.
Synchronous to MCLK in absence of signal at RTIP and RRING.
RD (DS)
2 I
Read Input (Data Strobe), Active Low. DS is active low when in
nonmultiplexed, Motorola mode. See the bus timing diagrams in
Section 11.
RCL/
LOTC
25 O
Receive Carrier Loss/Loss of Transmit Clock. An output which
will toggle high during a receive carrier loss (CCR2.7 = 0) or will
toggle high if the TCLK pin has not been toggled for 5 µsec ± 2
µsec (CCR2.7 = 1). CCR2.7 defaults to logic 0 when in hardware
mode.
RNEG 39 O
Receive Negative Data. Updated on the rising edge (CCR2.0 = 0)
or the falling edge (CCR2.0 = 1) of RCLK with the bipolar data out
of the line interface. Set NRZE (CCR1.6) to a one for NRZ
applications. In NRZ mode, data will be output on RPOS while a
received error will cause a positive-going pulse synchronous with
RCLK at RNEG. See Section 6.4 for details.
RPOS 38 O
Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or
the falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the
line interface. Set NRZE (CCR1.6) to a one for NRZ applications. In
NRZ mode, data will be output on RPOS while a received error will
cause a positive-going pulse synchronous with RCLK at RNEG. See
Section 6.4 for details.
RTIP/
RRING
27/28 I
Receive Tip and Ring. Analog inputs for clock recovery circuitry.
These pins connect via a 1:1 transformer to the line. See Section 5
for details.
TCLK 43 I
Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to
clock data through the transmit side formatter. Can be sourced
internally by MCLK or RCLK. See Common Control Register 1 and
Figure 1-3.
TEST 26 I
Tri-State Control. Set high to tri-state all outputs and I/O pins
(including the parallel control port). Set low for normal operation.
Useful in board level testing.
TNEG 42 I
Transmit Negative Data. Sampled on the falling edge (CCR2.1 =
0) or the rising edge (CCR2.1 = 1) of TCLK for data to be
transmitted out onto the line.
TPOS 41 I
Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0)
or the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted
out onto the line.