Datasheet

DS1977
5 of 29
Figure 2. HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL
1-Wire NET
OTHER
DEVICES
BUS
MASTER
DS1977
AVAILABLE
COMMANDS:
COMMAND
LEVEL:
DATA FIELD
AFFECTED:
1-Wire ROM FUNCTION
COMMANDS
READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
RESUME
OVERDRIVE SKIP
OVERDRIVE MATCH
64-BIT ROM, RC-FLAG
64-BIT ROM, RC-FLAG
64-BIT ROM, RC-FLAG
RC-FLAG
RC-FLAG
RC-FLAG, OD-FLAG
64-BIT ROM, RC-FLAG, OD-FLAG
DS1977-SPECIFIC
MEMORY FUNCTION
COMMANDS
WRITE SCRATCHPAD
READ SCRATCHPAD
COPY SCRATCHPAD
W/PW
READ MEMORY W/PW
VERIFY PASSWORD
READ VERSION
64-BYTE SCRATCHPAD
64-BYTE SCRATCHPAD
DATA MEMORY, PASSWORDS,
PASSWORD ENABLE BYTE
DATA MEMORY, PASSWORDS,
PASSWORD ENABLE BYTE
PASSWORDS
VERSION REGISTER
64-BIT LASERED ROM
Each DS1977 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next
48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. See Figure 3 for details. The 1-
Wire CRC is generated using a polynomial generator consisting of a Shift and XOR gates as shown in Figure 4.
The polynomial is X
8
+ X
5
+ X
4
+ 1. Additional information about the 1-Wire Cyclic Redundancy Check is available
in Application Note 27 and in the Book of DS19xx i
Button Standards.
The Shift register bits are initialized to 0. Then starting with the least significant bit of the family code, one bit at a
time is shifted in. After the 8
th
bit of the family code has been entered, then the serial number is entered. After the
48
th
bit of the serial number has been entered, the Shift register contains the CRC value. Shifting in the 8 bits of
CRC returns the Shift register to all 0s.
Figure 3. 64-BIT LASERED ROM
MSB
LSB
8-BIT
CRC CODE
48-BIT SERIAL NUMBER
8-BIT FAMILY
CODE (37h)
MSB LSB
MSB LSB
MSB LSB