Datasheet

DS1977
3 of 29
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Presence Detect
Sample Time
t
MSP
Standard speed, V
PUP
> 4.5V
(Note 1)
65 75
µs
Standard speed (Note 1)
68
75
Overdrive speed (Note 1)
7.5
10.5
I/O Pin, 1-Wire Write
Write-0 Low Time t
W0L
Standard speed (Notes 1, 13)
60
120
µs
Overdrive speed (Notes 1, 13)
6
16
Write-1 Low Time t
W1L
Standard speed (Notes 1, 13)
5
15
µs
Overdrive speed (Notes 1, 13)
1
2
I/O Pin, 1-Wire Read
Read Low Time t
RL
Standard speed (Notes 1, 14)
5
15 -
δ
µs
Overdrive speed (Notes 1, 14)
1
2 -
δ
Read Sample Time t
MSR
Standard speed,
V
PUP
> 4.5V (Notes 1, 14)
t
RL
+ δ
20
µs
Standard speed (Notes 1, 14)
t
RL
+
δ
15
Overdrive speed (Notes 1, 14)
t
RL
+
δ
2
I/O Pin, Strong Pullup
Strong Pullup Read
t
SPUR
(Note 1)
2.64
ms
Strong Pullup Write
t
SPUW
(Note 1)
22.46
ms
Strong Pullup password
verification
t
SPUV
(Note 1) 0.62 ms
EEPROM
Programming Current
I
LPROG
7
mA
Write/Erase Cycles
N
CYCLE
100k
—
Data Retention
t
RET
10
years
Note 1:
System requirement.
Note 2:
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded
systems, an active pullup such as that found in the DS2480B may be required.
Note 3:
Capacitance on the data pin could be 5nF when power is first applied.
Note 4:
V
TL
and V
TH
are functions of the internal supply voltage, which is a function of V
PUP
and the 1-Wire recovery times. The V
TH
and V
TL
maximum specifications are valid at V
PUPMAX
(5.25V). In any case, V
TL
< V
TH
< V
PUP
.
Note 5:
Voltage below which, during a falling edge on I/O, a logic '0' is detected.
Note 6:
The voltage on I/O needs to be less or equal to V
ILMAX
whenever the master drives the line low.
Note 7:
Voltage above which, during a rising edge on I/O, a logic '1' is detected.
Note 8:
After V
TH
is crossed during a rising edge on I/O, the voltage on I/O has to drop by V
HY
to be detected as logic '0'.
Note 9:
The I-V characteristic is linear for voltages less than 1V.
Note 10:
The earliest recognition of a negative edge is possible at t
REH
after V
TH
has been reached before.
Note 11:
Highlighted numbers are NOT in compliance with the published iButton standards. See comparison table below.
Note 12:
Interval during the negative edge on I/O at the beginning of a Presence Detect pulse between the time at which the voltage is 90%
of V
PUP
and the time at which the voltage is 10% of V
PUP
.
Note 13:
ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V
IL
to V
TH
. The actual maximum
duration for the master to pull the line low is t
W1LMAX
+ t
F
-
ε
and t
W0LMAX
+ t
F
-
ε
respectively.
Note 14:
δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V
IL
to the input-high threshold of
the bus master. The actual maximum duration for the master to pull the line low is t
RLMAX
+ t
F
.
Parameter
Name
Standard Values
DS1977 Values
Standard Speed
Overdrive Speed
Standard Speed
Overdrive Speed
min
max
min
max
min
max
min
max
t
SLOT
(incl. t
REC
)
61µs
(undef.)
7µs
(undef.)
65µs
1)
(undef.)
8µs
1)
(undef.)
t
RSTL
480µs
(undef.)
48µs
80µs
480µs
640µs
48µs
80µs
t
PDH
15µs
60µs
2µs
6µs
15µs
60µs
2.5µs
6.5µs
t
PDL
60µs
240µs
8µs
24µs
60µs
240µs
8µs
24µs
t
W0L
60µs
120µs
6µs
16µs
60µs
120µs
6µs
16µs
1) Intentional change, longer recovery time requirement due to modified 1-Wire front end.