Datasheet

DS1977
21 of 29
Figure 11. READ/WRITE TIMING DIAGRAM (continued)
Write-Zero Time Slot
RESISTOR MASTER
t
REC
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
t
F
t
SLOT
t
W0L
ε
Read-Data Time Slot
SLAVE-TO-MASTER
A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below V
TLMIN
until
the read low time t
RL
is expired. During the t
RL
window, when responding with a 0, the DS1977 will start pulling the
data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again.
When responding with a 1, the DS1977 will not hold the data line low at all, and the voltage starts rising as soon as
t
RL
is over.
The sum of t
RL
+ δ (rise rime) on one side and the internal timing generator of the DS1977 on the other side define
the master sampling window (t
MSRMIN
to t
MSRMAX
) in which the master must perform a read from the data line. For
most reliable communication, t
RL
should be as short as permissible and the master should read close to but no later
than t
MSRMAX
. After reading from the data line, the master must wait until t
SLOT
is expired. This guarantees sufficient
recovery time t
REC
for the DS1977 to get ready for the next time slot.
IMPROVED NETWORK BEHAVIOR
1-Wire networks can only be terminated during transients controlled by the bus master (1-Wire driver) and are
therefore susceptible to noise of various origins. Depending on the physical size and topology of the network,
reflections from end points and branch points can add up or cancel each other to some extent. Such reflections are
visible as glitches or ringing on the 1-Wire communication line. A glitch during the rising edge of a time slot can
cause a slave device to lose synchronization with the master and, as a consequence, result in a search ROM
command coming to a dead end. For better performance in network applications, the DS1977 uses a new 1-Wire
front end, which makes it less sensitive to noise and also reduces the magnitude of noise injected by the slave
device itself.
The 1-Wire front end of the DS1977 differs from traditional slave devices in four characteristics.
1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the line
impedance than a digitally switched transistor, converting the high frequency ringing known from traditional