Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsIntegrated Circuits (ICs)1 kBit 256 x 4

DS1972

1024-Bit EEPROM i

Button

________________________________________________________________

Maxim Integrated Products

19-4888; Rev 4; 1/12

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

General Description

The DS1972 is a 1024-bit, 1-Wire

EEPROM chip orga-

nized as four memory pages of 256 bits each in a

rugged iButton

package. Data is written to an 8-byte

scratchpad, verified, and then copied to the EEPROM

memory. As a special feature, the four memory pages

can individually be write protected or put in EPROM-

emulation mode, where bits can only be changed from

a 1 to a 0 state. The DS1972 communicates over the

single-conductor 1-Wire bus. The communication fol-

lows the standard 1-Wire protocol. Each device has its

own unalterable and unique 64-bit ROM registration

number that is factory lasered into the device. The reg-

istration number is used to address the device in a mul-

tidrop, 1-Wire net environment.

Applications

Access Control/Parking Meter

Work-in-Progress Tracking

Tool Management

Inventory Control

Maintenance/Inspection Data Storage

Features

♦ 1024 Bits of EEPROM Memory Partitioned Into

Four Pages of 256 Bits

♦ Individual Memory Pages Can Be Permanently

Write Protected or Put in EPROM-Emulation Mode

(“Write to 0”)

♦ Switchpoint Hysteresis and Filtering to Optimize

Performance in the Presence of Noise

♦ IEC 1000-4-2 Level 4 ESD Protection (±8kV

Contact, ±15kV Air, Typical)

♦ Reads and Writes Over a Wide Voltage Range

from 2.8V to 5.25V from -40°C to +85°C

♦ Communicates to Host with a Single Digital

Signal at 15.4kbps or 125kbps Using 1-Wire

Protocol

Common iButton Features

♦ Unique Factory-Lasered 64-Bit Registration

Number Ensures Error-Free Device Selection and

Absolute Traceability Because No Two Parts are

Alike

♦ Built-In Multidrop Controller for 1-Wire Net

♦ Chip-Based Data Carrier Stores Digital

Identification and Information, Armored in a

Durable Stainless-Steel Case

♦ Data Can Be Accessed While Affixed to Object

♦ Button Shape is Self-Aligning with Cup-Shaped

Probes

♦ Easily Affixed with Self-Stick Adhesive Backing,

Latched by its Flange, or Locked with a Ring

Pressed Onto its Rim

♦ Presence Detector Acknowledges When Reader

First Applies Voltage

Ordering Information

16.25mm

5.89mm

0.51mm

3.10mm

0.51mm

17.35mm

BRANDING

F5 SIZE

GND

IOIO

F3 SIZE

52 2D

0000006234FB

1-Wire

Pin Configurations

Denotes a lead(Pb)-free/RoHS-compliant package.

PART TEMP RANGE PIN-PACKAGE

DS1972-F5+ -40°C to +85°C F5 i

Button

DS1972-F3+ -40°C to +85°C F3 iButton

Examples of Accessories

PART ACCESSORY

DS9096P Self-Stick Adhesive Pad

DS9101 Multipurpose Clip

DS9093RA Mounting Lock Ring

DS9093A Snap-In Fob

DS9092 iButton Probe

1-Wire and i

Button are registered trademarks of Maxim

Integrated Products, Inc.

Summary of content (23 pages)

PAGE 1
9-4888; Rev 4; 1/12 1024-Bit EEPROM iButton The DS1972 is a 1024-bit, 1-Wire® EEPROM chip organized as four memory pages of 256 bits each in a rugged iButton® package. Data is written to an 8-byte scratchpad, verified, and then copied to the EEPROM memory. As a special feature, the four memory pages can individually be write protected or put in EPROMemulation mode, where bits can only be changed from a 1 to a 0 state. The DS1972 communicates over the single-conductor 1-Wire bus.
PAGE 2
DS1972 1024-Bit EEPROM iButton ABSOLUTE MAXIMUM RATINGS IO Voltage Range to GND .......................................-0.5V to +6V IO Sink Current ...................................................................20mA Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................
PAGE 3
1024-Bit EEPROM iButton (TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN: 1-Wire WRITE Write-Zero Low Time (Notes 2, 16, 17) Write-One Low Time (Notes 2, 17) tW0L tW1L Standard speed 60 120 Overdrive speed, VPUP > 4.5V 5 15.5 Overdrive speed 6 15.
PAGE 4
DS1972 1024-Bit EEPROM iButton Note 19: Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO during the programming interval should be such that the voltage at IO is greater than or equal to VPUPMIN. If VPUP in the system is close to VPUPMIN, a lowimpedance bypass of RPUP, which can be activated during programming, may need to be added.
PAGE 5
1024-Bit EEPROM iButton The DS1972 combines 1024 bits of EEPROM, an 8-byte register/control page with up to 7 user read/write bytes, and a fully featured 1-Wire interface in a rugged iButton package. Each DS1972 has its own 64-bit ROM registration number that is factory lasered into the chip to provide a guaranteed unique identity for absolute traceability. Data is transferred serially through the 1Wire protocol, which requires only a single data contact and a ground return.
PAGE 6
DS1972 1024-Bit EEPROM iButton MSB LSB 8-BIT CRC CODE MSB 8-BIT FAMILY CODE (2Dh) 48-BIT SERIAL NUMBER LSB MSB LSB MSB LSB Figure 3. 64-Bit Lasered ROM POLYNOMIAL = X8 + X5 + X4 + 1 1ST STAGE X0 2ND STAGE X1 3RD STAGE X2 4TH STAGE X3 5TH STAGE X4 6TH STAGE X5 7TH STAGE X6 8TH STAGE X7 X8 INPUT DATA Figure 4. 1-Wire CRC Generator commands is described in Figure 9.
PAGE 7
1024-Bit EEPROM iButton Data memory and registers are located in a linear address space, as shown in Figure 5. The data memory and the registers have unrestricted read access. The DS1972 EEPROM array consists of 18 rows of 8 bytes each. The first 16 rows are divided equally into four memory pages (32 bytes each). These four pages are the primary data memory. Each page can be individually set to open (unprotected), write protected, or EPROM mode by setting the associated protection byte in the register row.
PAGE 8
DS1972 1024-Bit EEPROM iButton The protection-control registers determine how incoming data on a Write Scratchpad command is loaded into the scratchpad. A protection setting of 55h (write protect) causes the incoming data to be ignored and the target address main memory data to be loaded into the scratchpad. A protection setting of AAh (EPROM mode) causes the logical AND of incoming data and target address main memory data to be loaded into the scratchpad.
PAGE 9
1024-Bit EEPROM iButton Memory Function Commands The Memory Function Flowchart (Figure 7) describes the protocols necessary for accessing the memory of the DS1972. An example on how to use these functions to write to and read from the device is in the Memory Function Example section. The communication between the master and the DS1972 takes place either at standard speed (default, OD = 0) or at overdrive speed (OD = 1). If not explicitly set into overdrive mode, the DS1972 assumes standard speed.
PAGE 10
DS1972 1024-Bit EEPROM iButton FROM ROM FUNCTIONS FLOWCHART (FIGURE 9) BUS MASTER Tx MEMORY FUNCTION COMMAND 0Fh WRITE SCRATCHPAD? AAh READ SCRATCHPAD? N Y Y BUS MASTER Tx TA1 (T[7:0]), TA2 (T[15:8]) BUS MASTER Rx TA1 (T[7:0]), TA2 (T[15:8]), AND E/S BYTE DS1972 SETS PF = 1 CLEARS AA = 0 SETS E[2:0] = T[2:0] DS1972 SETS SCRATCHPAD BYTE COUNTER = T[2:0] MASTER Tx DATA BYTE TO SCRATCHPAD DS1972 INCREMENTS E[2:0] MASTER Tx RESET? APPLIES ONLY IF THE MEMORY AREA IS NOT PROTECTED.
PAGE 11
1024-Bit EEPROM iButton 55h COPY SCRATCHPAD? Y Y BUS MASTER Tx TA1 (T[7:0]), TA2 (T[15:8]) ADDRESS < 90h? Y T[15:0] < 0090h? N Y APPLICABLE TO ALL R/W MEMORY LOCATIONS. BUS MASTER Tx TA1 (T[7:0]), TA2 (T[15:8]) AND E/S BYTE AUTH.
PAGE 12
DS1972 1024-Bit EEPROM iButton Copy Scratchpad [55h] The Copy Scratchpad command is used to copy data from the scratchpad to writable memory sections. After issuing the Copy Scratchpad command, the master must provide a 3-byte authorization pattern, which should have been obtained by an immediately preceding Read Scratchpad command. This 3-byte pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order).
PAGE 13
1024-Bit EEPROM iButton DS1972 VPUP BUS MASTER DS1972 1-Wire PORT RPUP DATA Rx Tx Rx = RECEIVE Tx = TRANSMIT OPEN-DRAIN PORT PIN Rx IL Tx 100Ω MOSFET Figure 8. Hardware Configuration Initialization All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s).
PAGE 14
DS1972 1024-Bit EEPROM iButton BUS MASTER Tx RESET PULSE FROM FIGURE 9b FROM MEMORY FUNCTIONS FLOWCHART (FIGURE 7) OD RESET PULSE? N OD = 0 Y BUS MASTER Tx ROM FUNCTION COMMAND 33h READ ROM COMMAND? DS1972 Tx PRESENCE PULSE N 55h MATCH ROM COMMAND? F0h SEARCH ROM COMMAND? N N CCh SKIP ROM COMMAND? Y Y Y Y RC = 0 RC = 0 RC = 0 RC = 0 DS1972 Tx FAMILY CODE (1 BYTE) MASTER Tx BIT 0 TO FIGURE 9b DS1972 Tx BIT 0 DS1972 Tx BIT 0 MASTER Tx BIT 0 BIT 0 MATCH? N N BIT 0 MATCH? Y Y DS1
PAGE 15
1024-Bit EEPROM iButton DS1972 TO FIGURE 9a FROM FIGURE 9a A5h RESUME COMMAND? 3Ch OVERDRIVESKIP ROM? N Y N Y N Y RC = 0; OD = 1 RC = 1? 69h OVERDRIVEMATCH ROM? RC = 0; OD = 1 N Y MASTER Tx BIT 0 (SEE NOTE) MASTER Tx RESET? N Y BIT 0 MATCH? N OD = 0 Y MASTER Tx BIT 1 MASTER Tx RESET? N Y (SEE NOTE) BIT 1 MATCH? N OD = 0 Y MASTER Tx BIT 63 (SEE NOTE) BIT 63 MATCH? N OD = 0 Y FROM FIGURE 9a RC = 1 TO FIGURE 9a NOTE: THE OD FLAG REMAINS AT 1 IF THE DEVICE WAS ALREADY AT OVE
PAGE 16
DS1972 1024-Bit EEPROM iButton Resume [A5h] To maximize the data throughput in a multidrop environment, the Resume command is available. This command checks the status of the RC bit and, if it is set, directly transfers control to the memory function commands, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM, or Overdrive-Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the Resume command.
PAGE 17
1024-Bit EEPROM iButton DS1972 MASTER Tx "RESET PULSE" MASTER Rx "PRESENCE PULSE" ε tMSP VPUP VIHMASTER VTH VTL VILMAX 0V tRSTL tPDH tF tPDL tREC tRSTH RESISTOR MASTER DS1972 Figure 10. Initialization Procedure: Reset and Presence Pulse Read/Write Time Slots Data communication with the DS1972 takes place in time slots that carry a single bit each. Write time slots transport data from bus master to slave. Read time slots transfer data from slave to master.
PAGE 18
DS1972 1024-Bit EEPROM iButton WRITE-ONE TIME SLOT tW1L VPUP VIHMASTER VTH VTL VILMAX 0V ε tF tSLOT RESISTOR MASTER WRITE-ZERO TIME SLOT tW0L VPUP VIHMASTER VTH VTL VILMAX 0V ε tF tREC tSLOT RESISTOR MASTER READ-DATA TIME SLOT tMSR tRL VPUP VIHMASTER VTH MASTER SAMPLING WINDOW VTL VILMAX 0V δ tF tREC tSLOT RESISTOR MASTER DS1972 Figure 11.
PAGE 19
1024-Bit EEPROM iButton In a 1-Wire environment, line termination is possible only during transients controlled by the bus master (1-Wire driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the physical size and topology of the network, reflections from end points and branch points can add up or cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line.
PAGE 20
DS1972 1024-Bit EEPROM iButton POLYNOMIAL = X16 + X15 + X2 + 1 1ST STAGE 3RD STAGE 2ND STAGE X0 X2 X1 9TH STAGE X8 4TH STAGE 10TH STAGE X9 11TH STAGE X10 X3 12TH STAGE X11 5TH STAGE 6TH STAGE X4 13TH STAGE X12 X5 14TH STAGE X13 7TH STAGE X6 8TH STAGE X7 15TH STAGE X14 16TH STAGE X15 X16 CRC OUTPUT INPUT DATA Figure 13. CRC-16 Hardware Description and Polynomial by the bus master. The DS1972 transmits this CRC only if E[2:0] = 111b.
PAGE 21
1024-Bit EEPROM iButton Master to Slave Slave to Master Programming 1-Wire Communication Examples Write Scratchpad (Cannot Fail) RST PD Select WS TA <8–T[2:0] bytes> CRC-16 FF Loop Read Scratchpad (Cannot Fail) RST PD Select RS TA-E/S <8–T[2:0] bytes> CRC-16 FF Loop Copy Scratchpad (Success) RST PD Select CPS TA-E/S Programming AA Loop Copy Scratchpad (Invalid Address or PF = 1 or Copy Protected) RST PD Select CPS TA-E/S FF Loop Read Memory (Success) RST PD Select RM TA FF Loop Read
PAGE 22
DS1972 1024-Bit EEPROM iButton Memory Function Example Write to the first 8 bytes of memory page 1. Read the entire memory.
PAGE 23
1024-Bit EEPROM iButton REVISION NUMBER REVISION DATE 0 4/06 Initial release 1 8/06 UL#913 bullet changed from “Meets UL#93 (4th Edit.). . .(Application Pending)” to “Designed to meet UL#93 (4th Edit.). . .” 2 8/09 3 4 4/10 1/12 DESCRIPTION PAGES CHANGED — 1, 2 Deleted UL#913 bullet from the Common iButton Features section. 1 Changed the RoHS packages to lead(Pb)-free packages in the Ordering Information table. 1 Changed VTLMIN from 0.46V to 0.5V in the Electrical Characteristics table.