Datasheet

Data in the EEPROM registers is retained when the
device is powered down; at power-up the EEPROM data
is reloaded into the corresponding scratchpad locations.
Data can also be reloaded from EEPROM to the scratch-
pad at any time using the Recall E
2
[B8h] command.
The master can issue “read-time slots” (see the 1-Wire
Bus System section) following the Recall E
2
command
and the DS18S20 will indicate the status of the recall by
transmitting 0 while the recall is in progress and 1 when
the recall is done.
CRC Generation
CRC bytes are provided as part of the DS18S20’s 64-bit
ROM code and in the 9th byte of the scratchpad memory.
The ROM code CRC is calculated from the first 56 bits
of the ROM code and is contained in the most significant
byte of the ROM. The scratchpad CRC is calculated from
the data stored in the scratchpad, and therefore it chang-
es when the data in the scratchpad changes. The CRCs
provide the bus master with a method of data validation
when data is read from the DS18S20. To verify that data
has been read correctly, the bus master must re-calculate
the CRC from the received data and then compare this
value to either the ROM code CRC (for ROM reads) or
to the scratchpad CRC (for scratchpad reads). If the cal-
culated CRC matches the read CRC, the data has been
received error free. The comparison of CRC values and
the decision to continue with an operation are determined
entirely by the bus master. There is no circuitry inside the
DS18S20 that prevents a command sequence from pro-
ceeding if the DS18S20 CRC (ROM or scratchpad) does
not match the value generated by the bus master.
The equivalent polynomial function of the CRC (ROM or
scratchpad) is:
CRC = X
8
+ X
5
+ X
4
+ 1
The bus master can re-calculate the CRC and compare it
to the CRC values from the DS18S20 using the polyno-
mial generator shown in Figure 10. This circuit consists
of a shift register and XOR gates, and the shift register
bits are initialized to 0. Starting with the least significant
bit of the ROM code or the least significant bit of byte 0
in the scratchpad, one bit at a time should shifted into the
shift register. After shifting in the 56th bit from the ROM or
the most significant bit of byte 7 from the scratchpad, the
polynomial generator will contain the re-calculated CRC.
Next, the 8-bit ROM code or scratchpad CRC from the
DS18S20 must be shifted into the circuit. At this point, if
the re-calculated CRC was correct, the shift register will
contain all 0s. Additional information about the Maxim
1-Wire cyclic redundancy check is available in Application
Note 27: Understanding and Using Cyclic Redundancy
Checks with Maxim ịButton Products.
1-Wire Bus System
The 1-Wire bus system uses a single bus master to con-
trol one or more slave devices. The DS18S20 is always a
slave. When there is only one slave on the bus, the sys-
tem is referred to as a “single-drop” system; the system is
“multidrop” if there are multiple slaves on the bus.
All data and commands are transmitted least significant
bit first over the 1-Wire bus.
The following discussion of the 1-Wire bus system is
broken down into three topics: hardware configuration,
transaction sequence, and 1-Wire signaling (signal types
and timing).
Figure 10. CRC Generator
(MSB) (LSB)
XOR
XOR
XOR
INPUT
DS18S20 High-Precision 1-Wire Digital Thermometer
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