Datasheet

DS18S20
14 of 23
READ-TIME SLOTS
The DS18S20 can only transmit data to the master when the master issues read-time slots. Therefore, the
master must generate read-time slots immediately after issuing a Read Scratchpad [BEh] or Read Power
Supply [B4h] command, so that the DS18S20 can provide the requested data. In addition, the master can
generate read-time slots after issuing Convert T [44h] or Recall E
2
[B8h] commands to find out the status
of the operation as explained in the DS18S20 Function Commands section.
All read-time slots must be a minimum of 60µs in duration with a minimum of a 1µs recovery time
between slots. A read-time slot is initiated by the master device pulling the 1-Wire bus low for a
minimum of 1µs and then releasing the bus (see Figure 11). After the master initiates the read-time slot,
the DS18S20 will begin transmitting a 1 or 0 on bus. The DS18S20 transmits a 1 by leaving the bus high
and transmits a 0 by pulling the bus low. When transmitting a 0, the DS18S20 will release the bus by the
end of the time slot, and the bus will be pulled back to its high idle state by the pullup resister. Output
data from the DS18S20 is valid for 15µs after the falling edge that initiated the read-time slot. Therefore,
the master must release the bus and then sample the bus state within 15µs from the start of the slot.
Figure 12 illustrates that the sum of T
INIT
, T
RC
, and T
SAMPLE
must be less than 15µs for a read-time slot.
Figure 13 shows that system timing margin is maximized by keeping T
INIT
and T
RC
as short as possible
and by locating the master sample time during read-time slots towards the end of the 15µs period.
Figure 11. Read/Write Time Slot Timing Diagram
45
µ
s
15
µ
s
V
PU
GND
1-WIRE BUS
60µs < T
X
“0” < 120µs
1
µ
s < T
REC
< ∞
DS18S20 Samples
MIN TYP MAX
15µs
30µs
> 1
µ
s
MASTER WRITE “0” SLOT MASTER WRITE “1” SLOT
V
PU
GND
1-WIRE BUS
15µs
MASTER READ “0” SLOT
MASTER READ “1” SLOT
Master samples
Master samples
START
OF SLOT
START
OF SLOT
> 1
µ
s
1
µ
s < T
REC
< ∞
15µs
15µs
30µs
15
µ
s
DS18S20 Samples
MIN TYP MAX
> 1µs
LINE TYPE LEGEND
Bus master pulling low DS18S20 pulling low
Resistor pullup