Datasheet

DS18S20-PAR
15 of 20
release the bus by the end of the time slot, and the bus will be pulled back to its high idle state by the
pullup resister. Output data from the DS18S20-PAR is valid for 15 ms after the falling edge that initiated
the read time slot. Therefore, the master must release the bus and then sample the bus state within 15 ms
from the start of the slot.
Figure 13 illustrates that the sum of T
INIT
, T
RC
, and T
SAMPLE
must be less than 15 ms for a read time slot.
Figure 14 shows that system timing margin is maximized by keeping T
INIT
and T
RC
as short as possible
and by locating the master sample time during read time slots towards the end of the 15 ms period.
DETAILED MASTER READ 1 TIMING Figure 13
RECOMMENDED MASTER READ 1 TIMING Figure 14
V
PU
GND
1-WIRE BUS
15 ms
V
IH of Master
T
RC
T
INT
> 1 ms
Master samples
LINE TYPE LEGEND
Bus master pulling low
Resistor pullup
V
PU
GND
1-WIRE BUS
15 ms
V
IH of Master
T
RC
=
small
T
INT
=
small
Master samples