Datasheet

DS18S20-PAR
14 of 20
The DS18S20-PAR samples the 1-Wire bus during a window that lasts from 15 ms to 60 ms after the
master initiates the write time slot. If the bus is high during the sampling window, a 1 is written to the
DS18S20-PAR. If the line is low, a 0 is written to the DS18S20-PAR.
READ/WRITE TIME SLOT TIMING DIAGRAM Figure 12
READ TIME SLOTS
The DS18S20-PAR can only transmit data to the master when the master issues read time slots.
Therefore, the master must generate read time slots immediately after issuing a Read Scratchpad [BEh]
command, so that the DS18S20-PAR can provide the requested data. In addition, the master can generate
read time slots after issuing a Recall E
2
[B8h] command to find out the recall status as explained in the
DS18S20-PAR FUNCTION COMMAND section.
All read time slots must be a minimum of 60 ms in duration with a minimum of a 1 ms recovery time
between slots. A read time slot is initiated by the master device pulling the 1-Wire bus low for a
minimum of 1 ms and then releasing the bus (see Figure 12). After the master initiates the read time slot,
the DS18S20-PAR will begin transmitting a 1 or 0 on bus. The DS18S20-PAR transmits a 1 by leaving
the bus high and transmits a 0 by pulling the bus low. When transmitting a 0, the DS18S20-PAR will
LINE TYPE LEGEND
Bus master pulling low DS18S20-PAR pulling low
Resistor pullup
45 ms
15 ms
V
PU
GND
1-WIRE BUS
60 ms < T
X
“0” < 120
1 ms < T
REC
< ¥
DS18S20-PAR samples
MIN TYP MA
X
15 ms
30 ms
> 1 ms
MASTER WRITE “0” SLOT MASTER WRITE “1” SLOT
DS18S20-PAR samples
MIN TYP MA
X
V
PU
GND
1-WIRE BUS
15 ms
MASTER READ “0” SLOT MASTER READ “1” SLOT
Master samples
Master samples
START
OF SLOT
START
OF SLOT
> 1 ms
1 ms < T
REC
< ¥
15 ms
15 ms
30 ms
15 ms
> 1 ms