Datasheet

DS18B20-PAR
15 of 19
the read time slot. Therefore, the master must release the bus and then sample the bus state within 15 μs
from the start of the slot.
Figure 14 illustrates that the sum of T
INIT
, T
RC
, and T
SAMPLE
must be less than 15 μs for a read time slot.
Figure 15 shows that system timing margin is maximized by keeping T
INIT
and T
RC
as short as possible
and by locating the master sample time during read time slots towards the end of the 15 μs period.
DETAILED MASTER READ 1 TIMING Figure 14
RECOMMENDED MASTER READ 1 TIMING Figure 15
DS18B20-PAR OPERATION EXAMPLE 1
In this example there are multiple DS18B20-PARs on the bus. The bus master initiates a temperature
conversion in a specific DS18B20-PAR and then reads its scratchpad and recalculates the CRC to verify
the data.
MASTER MODE DATA (LSB FIRST) COMMENTS
TX Reset Master issues reset pulse.
RX Presence DS18B20-PARs respond with presence pulse.
TX 55h Master issues Match ROM command.
TX 64-bit ROM code Master sends DS18B20-PAR ROM code.
TX 44h Master issues Convert T command.
TX DQ line held high by
strong pullup
Master applies strong pullup to DQ for the duration of the
conversion (t
conv
).
TX Reset Master issues reset pulse.
RX Presence DS18B20-PARs respond with presence pulse.
TX 55h Master issues Match ROM command.
TX 64-bit ROM code Master sends DS18B20-PAR ROM code.
TX BEh Master issues Read Scratchpad command.
V
PU
GND
1-WIRE BUS
15
μ
s
VIH of Master
T
RC
T
INT
> 1 μs
Master samples
LINE TYPE LEGEND
Bus master pulling low
Resistor pullup
V
PU
GND
1-WIRE BUS
15
μ
s
VIH of Master
T
RC
=
small
T
INT
=
small
Master samples