Datasheet

DS1886
SFP and PON ONU Controller
with Digital LDD Interface
8Maxim Integrated
Figure 1a. ADC Channel Only for TXP when BURST_MODE = 1 in Table 02h, Register 89h .................. 19
Figure 1b. ADC Channel
....................................................................... 19
Figure 2. ADC Round-Robin Timing
............................................................... 21
Figure 3. RSSI Differential Input for High-Side RSSI
.................................................. 21
Figure 4. Laser Bias (TXB) and Laser Power (TXP) Monitoring Through TXMON
........................... 22
Figure 5. RSSI in APD Mode
.................................................................... 22
Figure 6. RSSI in PIN Mode
..................................................................... 23
Figure 7. Low-Voltage Hysteresis Example
......................................................... 24
Figure 9. Delta-Sigma Output
................................................................... 25
Figure 8. Recommended Shunt Reference and RC Filter for DAC Output
................................. 25
Figure 10. TXFOUT and TXDOUT Logic Diagram.
................................................... 26
Figure 11. RSEL Logic Diagram
.................................................................. 26
Figure 12a. TXFOUT Nonlatched Operation
........................................................ 27
Figure 12b. TXFOUT Latched
................................................................... 27
Figure 12c. TXFOUT During Power-On
............................................................ 27
Figure 13. 3-Wire Interface Timing Diagram
........................................................ 28
Figure 14. 3-Wire Flowchart
.....................................................................30
Figure 15. MAX3710 Brownout Detection Flowchart
.................................................. 31
Figure 16. Offset LUT
.......................................................................... 34
Figure 17. MODULATION LUT (Open Loop and APC Mode)
........................................... 34
Figure 18. BIAS LUT (Open Loop)
................................................................ 34
Figure 19. I
2
C Timing Diagram ..................................................................36
Figure 20. Example I
2
C Timing .................................................................. 37
Figure 21. Memory Organization
................................................................. 39
LIST OF FIGURES