Datasheet

DS1886
SFP and PON ONU Controller
with Digital LDD Interface
59Maxim Integrated
A2h Table 01h, Register FCh: WARN EN
3
POWER-ON VALUE 00h
READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS PW2 or (PW1 and RWTBL1C)
MEMORY TYPE Nonvolatile (SEE)
FCh TEMP HI TEMP LO VCC HI VCC LO TXB HI TXB LO TXP HI TXP LO
BIT 7 BIT 0
Layout is identical to WARN
3
in Lower Memory, Register 74h. Enables warnings to create TXFINT (Lower Memory,
Register 71h) logic. The MASK bit (A2h Table 02h, Register 89h) determines whether this memory exists in A2h
Table 01h or 05h. When in A2h Table 05h, this location at A2h Table 01h becomes EE.
BIT 7
TEMP HI:
0 = Disables interrupt from TEMP HI warning.
1 = Enables interrupt from TEMP HI warning.
BIT 6
TEMP LO:
0 = Disables interrupt from TEMP LO warning.
1 = Enables interrupt from TEMP LO warning.
BIT 5
VCC HI:
0 = Disables interrupt from VCC HI warning.
1 = Enables interrupt from VCC HI warning.
BIT 4
VCC LO:
0 = Disables interrupt from VCC LO warning.
1 = Enables interrupt from VCC LO warning.
BIT 3
TXB HI:
0 = Disables interrupt from TXB HI warning.
1 = Enables interrupt from TXB HI warning.
BIT 2
TXB LO:
0 = Disables interrupt from TXB LO warning.
1 = Enables interrupt from TXB LO warning.
BIT 1
TXP HI:
0 = Disables interrupt from TXP HI warning.
1 = Enables interrupt from TXP HI warning.
BIT 0
TXP LO:
0 = Disables interrupt from TXP LO warning.
1 = Enables interrupt from TXP LO warning.