Datasheet

DS1886
SFP and PON ONU Controller
with Digital LDD Interface
52Maxim Integrated
A2h Lower Memory, Register 71h: ALARM
2
A2h Lower Memory, Register 72h–73h: RESERVED
POWER-ON VALUE 00h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE Volatile
71h RSSI HI RSSI LO RESERVED RESERVED RESERVED IN1S RESERVED TXFINT
BIT 7 BIT 0
BIT 7
RSSI HI: High alarm status for RSSI measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 6
RSSI LO: Low alarm status for RSSI measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BITS 5:3
RESERVED
BIT 2
IN1S: IN1 status bit. Reflects the logic state of the IN1 pin (read-only).
0 = IN1 pin is logic-low.
1 = IN1 pin is logic-high.
BIT 1
RESERVED
BIT 0
TXFINT: TXFOUT interrupt. This bit is the wired-ORed logic of all alarms and warnings wired-ANDed with
their corresponding enable bits. The enable bits are found in A2h Table 01h/05h, Registers F8–FFh.
POWER-ON VALUE 00h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE
These registers are reserved.