Datasheet

DS1886
SFP and PON ONU Controller
with Digital LDD Interface
50Maxim Integrated
A2h Lower Memory, Register 6Fh: UPDATE
POWER-ON VALUE 00h
READ ACCESS All
WRITE ACCESS All and DS1886 Hardware
MEMORY TYPE Volatile
6Fh TEMP RDY VCC RDY TXB RDY TXP RDY RSSI RDY RSSIR POW_LEV1 POW_LEV0
BIT 7 BIT 0
BITS 7:3
Update of completed conversions. At power-on, these bits are cleared and are set as each conversion is
completed. These bits can be cleared so that a completion of a new conversion is verified.
BIT 2
RSSIR: RSSI range. Reports the range used for conversion update of RSSI.
0 = Fine range is the reported value.
1 = Coarse range is the reported value.
BITS 1:0
POW_LEV[1:0]: Power level. These bits are active only when the DS1863_MODE bit in A2h Table 02h,
Register 8Dh (CNFGD) is 0. These bits change the MAX3710 bits KRMD[2:1] to adjust the MD input
impedance. See the Power Leveling section for more details.