Datasheet

DS1886
SFP and PON ONU Controller
with Digital LDD Interface
43Maxim Integrated
A2h Table 08h Register Map
A2h Table 09h Register Map
Auxiliary A0h Memory Register Map
The access codes represent the factory default values of PW_ENA (A2h Table 02h, Register C0h) and PW_ENB (A2h Table 02h,
Register C1h).
A2h TABLE 08h (INC LUT)
ROW
(HEX)
ROW NAME
WORD 0 WORD 1 WORD 2 WORD 3
BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
80–F7 EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY
F8–FF
<8>
INCROW INCBYTE INCBYTE INCBYTE INCBYTE INCBYTE INCBYTE INCBYTE INCBYTE
A2h TABLE 09h (DAC OFFSET LUT)
ROW
(HEX)
ROW NAME
WORD 0 WORD 1 WORD 2 WORD 3
BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
80–F7 EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY
F8–FF
<8>
DAC OFFSET DACOFF DACOFF DACOFF DACOFF DACOFF DACOFF DACOFF DACOFF
AUXILIARY MEMORY (A0h)
ROW
(HEX)
ROW NAME
WORD 0 WORD 1 WORD 2 WORD 3
BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
00–7F
<5>
AUX EE EE EE EE EE EE EE EE EE
80–FF
<5>
AUX EE EE EE EE EE EE EE EE EE
ACCESS
CODE
<0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>
Read
Access
See each
bit/byte
separately
All All All PW2 All N/A PW1 PW2 N/A PW2 All
Write
Access
PW2 N/A
All and
device
hardware
PW2 +
mode
bit
All All PW1 PW2 PW2 N/A PW1