Datasheet

DS1886
SFP and PON ONU Controller
with Digital LDD Interface
23Maxim Integrated
Figure 6. RSSI in PIN Mode
PIN Mode
The PIN mode is intended for systems with a linear rela-
tionship between the RSSI input and desired ADC result.
The ADC result transitions between the fine and coarse
ranges with hysteresis, as shown in Figure 6.
In PIN mode, the thresholds between coarse and fine
mode are a function of the number of right-shifts being
used. With the use of right-shifting, the fine mode full scale
is programmed to (1/2
nth
) of the coarse mode full scale.
The DS1886 now auto ranges to choose the range that
gives the best resolution for the measurement. Table 3
shows the threshold values for each possible number of
right-shifts.
Low-Voltage Operation
The DS1886 contains two power-on reset (POR) levels.
The lower level is a digital POR (POD) and the higher
level is an analog POR (POA). At startup, before the
supply voltage rises above POA, the outputs are dis-
abled, all SRAM locations are set to their defaults,
shadowed EEPROM locations are zero, and all analog
Table 3. RSSI Hysteresis Threshold Values
*This is the minimum reported coarse mode conversion.
Table 4. RSSI Configuration Registers
# OF RIGHT-
SHIFTS
FINE MODE
MAX (HEX)
COARSE MODE
MIN* (HEX)
0 FFF8h F000h
1 7FFCh 7800h
2 3FFEh 3C00h
3 1FFFh 1E00h
4 0FFFh 0F00h
5 07FFh 0780h
6 03FFh 03C0h
7 01FFh 01E0h
REGISTER FINE MODE COARSE MODE
Gain Register
(RSSI FINE/COARSE
SCALE)
98h–99h, A2h
Table 02h
9Ch–9Dh, A2h
Table 02h
Offset Register
(RSSI FINE/COARSE
OFFEST)
A8h–A9h, A2h
Table 02h
ACh–ADh, A2h
Table 02h
RIGHT-SHIFT
1
Register
8Eh, A2h
Table 02h
N/A
RSSIC and RSSIF Bits
(RIGHT-SHIFT
0
)
8Fh, A2h Table 02h
RSSIR Bit (UPDATE) 6Fh, A2h Lower Memory
RSSI Measurement
(RSSI VALUE)
68h–69h, A2h Lower Memory
PIN MODE
RSSI RESULT
FINE FULL-SCALE RESPONSE
COARSE FULL-SCALE RESPONSE
FINE RIGHT-SHIFT = 3
RSSI INPUT
FINE COARSE
HYSTERESIS