Datasheet

46 Maxim Integrated
SFP Controller for Dual Rx Interface
DS1877
Table 02h, Register 89h: CNFGB
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
A2h AND B2h MEMORY Common A2h and B2h memory locations
MEMORY TYPE Nonvolatile (SEE)
89h INXC INVOUTX ALATCH2 QTLATCH2 WLATCH2 ALATCH1 QTLATCH1 WLATCH1
BIT 7 BIT 0
BIT 7
INXC: INX software control bit (see Figure 11).
0 = INX pin’s logic controls OUTX pin.
1 = OUTX is active (bit 6 defines the polarity).
BIT 6
INVOUTX: Inverts the active state for OUTX (see Figure 11).
0 = Noninverted.
1 = Inverted.
BIT 5
ALATCH2: ADC alarm’s comparison latch, Lower Memory, Registers 70h–71h.
0 = ADC alarm and flags reflect the status of the last comparison.
1 = ADC alarm flags remain set.
BIT 4
QTLATCH2: QT’s comparison latch, Lower Memory, Register 73h.
0 = QT alarm and warning flags reflect the status of the last comparison.
1 = QT alarm and warning flags remain set.
BIT 3
WLATCH2: ADC warning’s comparison latch, Lower Memory, Register 74h.
0 = ADC warning flags reflect the status of the last comparison.
1 = ADC warning flags remain set.
BIT 2
ALATCH1: ADC alarm’s comparison latch, Lower Memory, Registers 70h–71h.
0 = ADC alarm and flags reflect the status of the last comparison.
1 = ADC alarm flags remain set.
BIT 1
QTLATCH1: QT’s comparison latch, Lower Memory, Register 73h.
0 = QT alarm and warning flags reflect the status of the last comparison.
1 = QT alarm and warning flags remain set.
BIT 0
WLATCH1: ADC warning’s comparison latch, Lower Memory, Register 74h.
0 = ADC warning flags reflect the status of the last comparison.
1 = ADC warning flags remain set.