Datasheet

13Maxim Integrated
SFP Controller for Dual Rx Interface
DS1877
Detailed Description
The DS1877 integrates the control and monitoring func-
tionality required in an SFP or SFP+ system. The device
is specifically designed for a dual-receiver SFP module.
Key components of the device are shown in the Block
Diagram and described in subsequent sections.
DACs During Power-Up
On power-up, the device sets the DACs to high imped-
ance. After time t
INIT
, the DACs are set to an initial con-
dition set in EEPROM. After a temperature conversion is
completed and if the VCC LO alarm is enabled, an addi-
tional V
CC
conversion above the customer-defined VCC
LO alarm level is required before the DACs are updated
with the value determined by the temperature conversion
and the DAC LUT. See Figure 1.
Quick-Trip Timing
As shown in Figure 2, the device’s input comparator is
shared between two LOS comparisons. The comparator
polls the alarms in a multiplexed sequence. The com-
parator checks the LOS (RSSI1_ and RSSI2_) signals
against the internal reference. Depending on the results
of the comparison, the corresponding alarms and warn-
ings are asserted or deasserted. Any QT alarm that is
detected by default remains active until a subsequent
comparator sample shows that the condition no longer
exists.
Table 1. Acronyms
Figure 1. Power-Up Timing
Figure 2. Quick-Trip Sample Timing
V
CC
V
POA
DAC
SETTINGS
HIGH IMPEDANCE OFF STATE LUT VALUE
500µs
t
INIT
QUICK-TRIP SAMPLE TIMES
LOS2 LOS1LOS1 LOS2
t
REP
ACRONYM DESCRIPTION
ADC Analog-to-Digital Converter
AGC Automatic Gain Control
APC Automatic Power Control
APD Avalanche Photodiode
ATB Alarm Trap Bytes
DAC Digital-to-Analog Converter
LOS Loss of Signal
LUT Lookup Table
NV Nonvolatile
QT Quick Trip
TIA Transimpedance Amplifier
ROSA Receiver Optical Subassembly
SEE Shadowed EEPROM
SFF Small Form Factor
SFF-8472
Document Defining Register Map of SFPs
and SFFs
SFP Small Form Factor Pluggable
SFP+ Enhanced SFP