Datasheet

DS1859
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
20 ____________________________________________________________________
MEMORY
LOCATION
(hex)
EEPROM/
SRAM
R/W
DEFAULT
SETTING
(hex)
NAME OF
LOCATION
FUNCTION
5——0 ADEN
Controls if the device responds to one or two device
addresses (see the Memory Description section and
Table 5).
4——0 ADFIX
Controls the means by which Main and Auxiliary Device
addresses are set (see the Memory Description section
and Table 5).
3——0 APEN
Controls auxiliary write protect. See the Memory
Description section.
2——0 MPEN
Controls main write protect. See the Memory Description
section.
1——0 INV1
Configures buffer 1 with OUT1 = MINT +
(INV1 [XOR] IN1).
0——0 INV2 Configures buffer 2 with OUT2 = INV2 [XOR] IN2.
8A to 8B
EEPROM
—— Reserved
8C
EEPROM
R/W A2
Device address
Contains Main Device address if the bit ADFIX = 1. If
ADFIX = 0, then address A2h is used.
8D
EEPROM
—— Reserved —
8E
EEPROM
R/W
Contains bits used to perform right shift operations on the
A/D output converter. See the Right Shift A/D Conversion
Result section.
7——0 —
6——0 MON1
2
Right Shift Control MSB
5——0 MON1
1
4——0 MON1
0
Right Shift Control LSB
3——0 —
2——0 MON2
2
Right Shift Control MSB
1——0 MON2
1
0——0 MON2
0
Right Shift Control LSB
8F
EEPROM
R/W
Contains bits used to perform right shift operations on the
A/D output converter. See the Right Shift A/D Conversion
Result section.
7——0 —
6——0 MON3
2
Right Shift Control MSB
5——0 MON3
1
4——0 MON3
0
Right Shift Control LSB
3——0 —
2——0 —
1——0 —
0——0 —
Table 01h (continued)