Datasheet
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
Maxim Integrated 5
DS1856
Note 10: After this period, the first clock pulse is generated.
Note 11: The maximum t
HD:DAT
only has to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
Note 12: A device must internally provide a hold time of at least 300ns for the SDA signal (see the V
IH MIN
of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 13: C
B
—total capacitance of one bus line, timing referenced to 0.9 x V
CC
and 0.1 x V
CC
.
Note 14: Guaranteed by design.
Typical Operating Characteristics
(V
CC
= 5.0V, T
A
= +25°C, for both 50kΩ and 20kΩ versions, unless otherwise noted.)
TEMPERATURE (°C)
40 60 80200-20
650
700
750
800
600
-40 100
SUPPLY CURRENT vs. TEMPERATURE
DS1856 toc01
SUPPLY CURRENT (μA)
SDA = SCL = V
CC
SUPPLY CURRENT vs. VOLTAGE
DS1856 toc02
VOLTAGE (V)
SUPPLY CURRENT (μA)
5.04.54.03.5
450
500
600
550
700
650
750
800
400
3.0 5.5
SDA = SCL = V
CC
RESISTANCE vs. SETTING
DS1856 toc03
SETTING (DEC)
RESISTANCE (kΩ)
20015010050
10
20
30
40
50
60
0
0 250
50kΩ VERSION
RESISTANCE vs. SETTING
DS1856 toc04
SETTING (DEC)
RESISTANCE (kΩ)
20015010050
5
10
15
20
0
0 250
20kΩ VERSION
ACTIVE SUPPLY CURRENT
vs. SCL FREQUENCY
DS1856 toc05
SCL FREQUENCY (kHz)
ACTIVE SUPPLY CURRENT (μA)
300200100
720
740
760
780
800
700
0 400
SDA = V
CC
RESISTOR 0 INL (LSB)
DS1856 toc06
SETTING (DEC)
RESISTOR 0 INL (LSB)
225200150 17550 75 100 12525
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 250