Datasheet
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
4 Maxim Integrated
DS1856
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Fast mode 0 400
SCL Clock Frequency (Note 9) f
SCL
Standard mode 0 100
kHz
Fast mode 1.3
Bus Free Time Between STOP and
START Condition (Note 9)
t
BUF
Standard mode 4.7
µs
Fast mode 0.6
Hold Time (Repeated)
START Condition (Notes 9, 10)
t
HD:STA
Standard mode 4.0
µs
Fast mode 1.3
LOW Period of SCL Clock (Note 9)
t
LOW
Standard mode 4.7
µs
Fast mode 0.6
H IG H P er i od of S C L C l ock ( N ote 9)
t
HIGH
Standard mode 4.0
µs
Fast mode 0 0.9
Data Hold Time (Notes 9, 11, 12)
t
HD:DAT
Standard mode 0
µs
Fast mode
100
Data Setup Time (Note 9)
t
SU:DAT
Standard mode
250
ns
Fast mode 0.6
START Setup Time (Note 9)
t
SU:STA
Standard mode 4.7
µs
Fast mode
20 + 0.1C
B
300
Rise Time of Both SDA and SCL
Signals (Note 13)
t
R
Standard mode
20 + 0.1C
B
1000
ns
Fast mode
20 + 0.1C
B
300
Fall Time of Both SDA and SCL
Signals (Note 13)
t
F
Standard mode
20 + 0.1C
B
300
ns
Fast mode 0.6
Setup Time for STOP Condition
t
SU:STO
Standard mode 4.0
µs
Capacitive Load for Each Bus Line
C
B
(Note 13) 400 pF
EEPROM Write Time t
W
10 20 ms
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.85V to 5.5V, T
A
= -40°C to +95°C, unless otherwise noted. See Figure 6.)
Note 1: All voltages are referenced to ground.
Note 2: I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if V
CC
is switched off.
Note 3: SDA and SCL are connected to V
CC
and all other input signals are connected to well-defined logic levels.
Note 4: Full scale is user programmable. The maximum voltage that the MON inputs read is approximately full scale, even if the volt-
age on the inputs is greater than full scale.
Note 5: This voltage defines the maximum range of the analog-to-digital converter voltage, not the maximum V
CC
voltage.
Note 6: Absolute linearity is the difference of measured value from expected value at DAC position. The expected value is a
straight line from measured minimum position to measured maximum position.
Note 7: Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change
is the slope of the straight line from measured minimum position to measured maximum position.
Note 8: See the
Typical Operating Characteristics
.
Note 9: A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
> 250ns must then be met. This
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line t
RMAX
+ t
SU:DAT
= 1000ns + 250ns = 1250ns
before the SCL line is released.