Datasheet

DS1842
76V, APD, Bias Output Stage with
Current Monitoring
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(T
A
= -40°C to +85°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 2: Rising MIROUT transition from 10µA to 1mA; V
MIRIN
= 40V, 2.5kΩ load.
Note 3: Guaranteed by design; not production tested.
Voltage Range on GATE and CLAMP
Relative to GND...................................................-0.3V to +12V
Voltage Range on MIRIN, MIROUT,
MIR1, and MIR2 Relative to GND........................-0.3V to +80V
Voltage Range on LX Relative to GND...................-0.3V to +85V
Continuous Power Dissipation (T
A
= +70°C)
TDFN (derate 24.4mW/°C above +70°C).................1951.2mW
Operating Junction Temperature Range...........-40°C to +150°C
Storage Temperature Range .............................-55°C to +135°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TDFN
Junction-to-Ambient Thermal Resistance (θ
JA
) ............41°C/W
Junction-to-Case Thermal Resistance (θ
JC
) ...................8°C/W
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Switching Frequency f
SW
0 1.2 MHz
C
GATE
V
GS
= 0V, V
DS
= 25V 40
FET Capacitance
C
LX
f
SW
= 1MHz 90
pF
FET Gate Resistance R
G
22 
V
GS
= 3V, I
D
= 170mA 4.6 10
FET On-Resistance R
DSON
V
GS
= 10V, I
D
= 170mA 3.7 8

GATE Voltage V
GS
0 11 V
Switching Current I
LX
Duty cycle = 10%, f
SW
= 100kHz 680 mA
LX Voltage V
LX
80 V
LX Leakage I
IL(LX)
V
GATE
= 0V, V
LX
= 76V -1 +1 μA
CLAMP Voltage V
CLAMP
0 11 V
CLAMP Threshold V
CLT
2 4 7 V
CLAMP = low 1.75 2.6 4 mA
Maximum MIROUT Current I
MIROUT
CLAMP = high 10 μA
I
MIROUT
= 1mA 0.095 0.100 0.105
I
MIROUT
= 1μA 0.094 0.100 0.106
MIR1 to MIROUT Ratio K
MIR1
15V < V
MIRIN
< 76V
A/A
I
MIROUT
= 1mA 0.190 0.200 0.210
I
MIROUT
= 1μA 0.188 0.200 0.212
MIR2 to MIROUT Ratio K
MIR2
15V < V
MIRIN
< 76V
A/A
MIR1, MIR2 Rise Time (20%/80%) t
RC
(Note 2) 30 ns
Shutdown Temperature T
SHDN
(Note 3) +150 °C
Leakage on GATE and CLAMP I
IL
-1 +1 μA
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial
.