Datasheet

DS1831/A/B

10 of 14

The ST input can be derived from many microprocessor outputs. The most typical signals used are the

microprocessor address signals, data signals, or control signals. When the microprocessor functions

normally, these signals would, as a matter of routine, cause the watchdog to be reset prior to time-out. To

guarantee that the watchdog timer does not time-out, a transition must occur at or less than the minimum

times shown in Table 1. A typical circuit example is shown in Figure 10. The watchdog timing is shown

in Figure 11.

The DS1831A watchdog function cannot be disabled. The watchdog strobe input must be strobed to avoid

a watchdog time-out however the watchdog status output can be disconnected yielding the same result.

WATCHDOG CIRCUIT EXAMPLE Figure 10

TIMING DIAGRAM — STROBE INPUT Figure 11

PBRST

3.3V

DS1831

GND

WDS

IN1

NMI1

SENSE1

µP

10kW

INVALID

EDGES

VALID

EDGES

INDETERMINATE

EDGES

MIN

MAX

WDS