Datasheet

DS1825 Programmable Resolution 1-Wire Digital Thermometer With 4-Bit ID
7 of 21
Figure 4. SUPPLYING THE PARASITE-POWERED DS1825 DURING
TEMPERATURE CONVERSIONS
Figure 5. POWERING THE DS1825 WITH AN EXTERNAL SUPPLY
64-BIT LASERED ROM CODE
Each DS1825 contains a unique 64-bit code (see Figure 6) stored in ROM. The least significant 8 bits of the ROM
code contain the DS1825’s 1-Wire family code: 3Bh. The next 48 bits contain a unique serial number. The most
significant 8 bits contain a cyclic redundancy check (CRC) byte that is calculated from the first 56 bits of the ROM
code. A detailed explanation of the CRC bits is provided in the CRC GENERATION section. The 64-bit ROM code
and associated ROM function control logic allow the DS1825 to operate as a 1-Wire device using the protocol
detailed in the 1-Wire BUS SYSTEM section of this data sheet.
Figure 6. 64-BIT LASERED ROM CODE
8-BIT CRC 48-BIT SERIAL NUMBER 8-BIT FAMILY CODE (3Bh)
MEMORY
The DS1825’s memory is organized as shown in Figure 7. The memory consists of an SRAM scratchpad with NV
EEPROM storage for the high and low alarm trigger registers (T
H
and T
L
) and configuration register. Note that if the
DS1825 alarm function is not used, the T
H
and T
L
registers can serve as general-purpose memory. All memory
commands are described in detail in the DS1825 FUNCTION COMMANDS section.
Byte 0 and byte 1 of the scratchpad contain the LSB and the MSB of the temperature register, respectively. These
bytes are read-only. Bytes 2 and 3 provide access to T
H
and T
L
registers. Byte 4 contains the configuration register
data, which is explained in detail in the CONFIGURATION REGISTER section of this data sheet. Bytes 5, 6, and 7
are reserved for internal use by the device and cannot be overwritten.
MSB MSB LSB LSB LSBMSB
V
PU
V
PU
4.7K
1-Wire Bus
Micro-
processor
DS1825
GND
V
DD
DQ
To Other
1-Wire
Devices
V
DD
(External Supply)
DS1825
GND
V
DD
DQ
V
PU
4.7K
To Other
1-Wire
Devices
1-Wire Bus
Micro-
processor