Datasheet

DS1822-PAR
15 of 19
resister. Output data from the DS1822-PAR is valid for 15μs after the falling edge that initiated the read-
time slots. Therefore, the master must release the bus and then sample the bus state within 15μs from the
start of the slot.
Figure 13 illustrates that the sum of T
INIT
, T
RC
, and T
SAMPLE
must be less than 15μs for a read-time slots.
Figure 14 shows that system timing margin is maximized by keeping T
INIT
and T
RC
as short as possible
and by locating the master sample time during read-time slots towards the end of the 15μs period.
DETAILED MASTER READ 1 TIMING Figure 13
RECOMMENDED MASTER READ 1 TIMING Figure 14
RELATED APPLICATION NOTES
The following Application Notes can be applied to the DS1822-PAR. These notes can be obtained from
the Dallas Semiconductor “Application Note Book,” via the Dallas website at http://www.dalsemi.com/,
or through our faxback service at [phone].
Application Note 27: Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor
Touch Memory Product
Application Note 55: Extending the Contact Range of Touch Memories
Application Note 74: Reading and Writing Touch Memories via Serial Interfaces
Application Note 104: Minimalist Temperature Control Demo
Application Note 106: Complex MicroLANs
Application Note 108: MicroLAN—In the Long Run
Application Note 162: Interfacing the DS18X20/DS1822 1-Wire Temperature Sensor in a
Microcontroller Environment
Sample 1-Wire subroutines that can be used in conjunction with AN74 can be downloaded from the
Dallas website or anonymous FTP Site.
V
PU
GND
1-WIRE BUS
15
μ
s
VIH of Master
T
RC
T
INT
> 1μs
Master samples
LINE TYPE LEGEND
Bus master pulling low
Resistor pullup
V
PU
GND
1-WIRE BUS
15
μ
s
VIH of Master
T
RC
=
small
T
INT
=
small
Master samples