Datasheet
DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
6 of 16
CLOCK ACCURACY (PowerCap MODULE)
The DS1744 and DS9034PCX are individually tested for accuracy. Once mounted together, the module
typically keeps time accuracy to within ±1.53 minutes per month (35ppm) at +25°C. Clock accuracy is
also affected by the electrical environment and caution should be taken to place the RTC in the lowest-
level EMI section of the PC board layout. For additional information, refer to Application Note 58:
Crystal Considerations with Maxim Real-Time Clocks.
Table 2. Register Map
ADDRESS
DATA
FUNCTION RANGE
B7
B6
B5
B4
B3
B2
B1
B0
7FFF
10 Year
Year
Year
00-99
7FFE X X X
10
Month
Month Month 01-12
7FFD
X
X
10 Date
Date
Date
01-31
7FFC
BF
FT
X
X
X
Day
Day
01-07
7FFB
X
X
10 Hour
Hour
Hour
00-23
7FFA
X
10 Minutes
Minutes
Minutes
00-59
7FF9
OSC
10 Seconds
Seconds
Seconds
00-59
7FF8
W
R
10 Century
Century
Century
00-39
OSC = Stop Bit
R = Read Bit
FT = Frequency Test
W = Write Bit
X = See Note
BF = Battery Flag
Note: All indicated “X” bits are not used but must be set to a “0” during write cycle to ensure proper clock operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1744 is in the read mode whenever
OE
(output enable) is low,
WE
(write enable) is high, and
CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address
locations in the NV SRAM. Valid data is available at the DQ pins within t
AA
after the last address input is
stable, providing that the
CE
and
OE
access times and states are satisfied. If
CE
or
OE
access times and
states are not met, valid data is available at the latter of chip-enable access (tCEA) or at output-enable access
time (tOEA). The state of the DQ pins is controlled by
CE
and
OE
. If the outputs are activated before tAA,
the data lines are driven to an intermediate state until tAA. If the address inputs are changed while
CE
and
OE
remain valid, output data remains valid for output-data hold time (tOH) but then goes indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1744 is in the write mode whenever
WE
and
CE
are in their active state. The start of a write is
referenced to the latter occurring transition of
WE
or
CE
. The addresses must be held valid throughout
the cycle.
CE
or
WE
must return inactive for a minimum of t
WR
prior to the initiation of another read or
write cycle. Data in must be valid t
DS
prior to the end of write and remain valid for t
DH
afterward. In a
typical application, the
OE
signal is high during a write cycle. However,
OE
can be active provided that
care is taken with the data bus to avoid bus contention. If
OE
is low prior to
WE
transitioning low, the
data bus can become active with read data defined by the address inputs. A low transition on
WE
then
disables the output t
WEZ
after
WE
goes active.