Datasheet

DS1683
Total-Elapsed-Time and Event Recorder with Alarm
13Maxim Integrated
REGISTERS 0Ah–0Dh: ETC REGISTER
REGISTERS 10h–11h: EVENT COUNTER ALARM LIMIT REGISTER
Factory Default 00 00 00 00h
Read Access All
Write Access PW
Memory Type Shadowed EEPROM, Nonvolatile
Memory
Access
R/W R/W R/W R/W R/W R/W R/W R/W
0Ah 2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
0Bh 2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
0Ch 2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
0Dh 2
31
2
30
2
29
2
28
2
27
2
26
2
25
2
24
BIT 7 BIT 0
The ETC register is a shadowed EEPROM register that contains the accumulated time in 250ms increments that the EVENT pin
has been held high. On power-up, on every rising edge of the EVENT pin, and after an I
2
C write to the ETC register, the value
from the shadowed EEPROM location is loaded into the ETC counter memory (SRAM). When the EVENT pin is high, it is this
SRAM memory that is incremented once every 250ms. On the falling edge of the EVENT pin, this value in SRAM memory is then
written to the shadowed EEPROM memory to store the accumulated time in 250ms increments.
Factory Default 00 00h
Read Access All
Write Access PW
Memory Type Shadowed EEPROM, Nonvolatile
Memory
Access
R/W R/W R/W R/W R/W R/W R/W R/W
10h 2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
11h 2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
BIT 7 BIT 0
The Event Counter Alarm Limit is a shadowed EEPROM register, and when the Event Counter register value equals or exceeds
the Event Counter Alarm Limit value, the EVENT flag bit (EVENT AF bit, Register 01h, bit 1) goes active high. When the Event
Counter register value drops below the Event Counter Alarm Limit value, the EVENT AF bit automatically clears.