Datasheet

2-Wire Serial Data Bus
The DS1631, DS1631A, and DS1731 communicate over
a bidirectional 2-wire serial data bus that consists of a
serial clock (SCL) signal and serial data (SDA) signal.
The DS1631, DS1631A, and DS1731 interface to the bus
through their SCL input pins and open-drain SDA I/O pins.
The following terminology is used to describe 2-wire com-
munication:
Master Device: Microprocessor/microcontroller that con-
trols the slave devices on the bus. The master device gen-
erates the SCL signal and START and STOP conditions.
Slave: All devices on the bus other than the master. The
DS1631, DS1631A, and DS1731 always function as
slaves.
Bus Idle or Not Busy: Both SDA and SCL remain high.
SDA is held high by a pullup resistor when the bus is idle,
and SCL must either be forced high by the master (if the
SCL output is push-pull) or pulled high by a pullup resistor
(if the SCL output is open-drain).
Transmitter: A device (master or slave) that is sending
data on the bus.
Receiver: A device (master or slave) that is receiving data
from the bus.
START Condition: Signal generated by the master to
indicate the beginning of a data transfer on the bus. The
master generates a START condition by pulling SDA from
high to low while SCL is high (see Figure 8). A “repeated”
START is sometimes used at the end of a data transfer
(instead of a STOP) to indicate that the master will per-
form another operation.
STOP Condition: Signal generated by the master to
indicate the end of a data transfer on the bus. The master
generates a STOP condition by transitioning SDA from low
to high while SCL is high (see Figure 8). After the STOP is
issued, the master releases the bus to its idle state.
Acknowledge (ACK): When a device is acting as a
receiver, it must generate an acknowledge (ACK) on the
SDA line after receiving every byte of data. The receiv-
ing device performs an ACK by pulling the SDA line low
for an entire SCL period (see Figure 8). During the ACK
clock cycle, the transmitting device must release SDA.
A variation on the ACK signal is the “not acknowledge”
(NACK). When the master device is acting as a receiver,
it uses a NACK instead of an ACK after the last data byte
to indicate that it is finished receiving data. The master
indicates a NACK by leaving the SDA line high during the
ACK clock cycle.
Slave Address: Every slave device on the bus has a
unique 7-bit address that allows the master to access
that device. The 7-bit bus address is 1 0 0 1 A
2
A
1
A
0
,
where A
2
, A
1
, and A
0
are user-selectable through the
corresponding input pins. The three address pins allow
up to eight DS1631s, DS1631As, or DS1731s to be mul-
tidropped on the same bus.
Control Byte: The control byte is transmitted by the mas-
ter and consists of the 7-bit slave address plus a read/
write (R/W) bit (see Figure 7). If the master is going to read
data from the slave device then R/W = 1, and if the master
is going to write data to the slave device then R/W = 0.
Command Byte: The command byte can be any of the
command protocols described in the Command Set sec-
tion of this data sheet.
Figure 7. Control Byte
Figure 8. START, STOP, and ACK signals
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
1 0 0 1 A
2
A
1
A
0
R/W
SDA
SCL
START
CONDITIONS
ACK (OR NACK)
FROM RECEIVER
STOP
CONDITION
DS1631/DS1631A/
DS1731
High-Precision Digital
Thermometer and Thermostat
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