Datasheet

DS1558

9 of 18

AM1 ALARM RATE

Table 3. ALARM MASK BITS

AM4 AM3 AM2

1 1 1 1 Once per second

1 1 1 0 Whe ec s man s ond tch

1 1 0 0 minutes and s match When second

1 0 0 hours, minutes, and seconds match 0 When

0 0 0 When date, hours, m s, and s s match 0 inute econd

W he R C regis atch alarm s, AF a 1. If AE is also set to a 1, the

a ond ac i

hen t T ter values m register setting is set to

larm c ition t vates the IRQ /FT pin. The IRQ /FT signal by a or write to the flags

is cleared read

hen

h is active, t e IRQ /FT si clear by having the address gnal can be ed

stable for as short as 15ns and either OE or

active, ut is teed e cleared unless t

fulfilled (F ess has been s

b not guaran to b

igure 2). Once the addr elected for at least 15ns, the IRQ al can be cleared

i ate ut is eed to be c til t

is re he alarm flag is also

c by ad or e flags reg the flag e s until the end of the

read/write cycle and the

/FT sign

mmedi ly, b not guarant leared un fulfilled (Figu 3). T

leared a re write to th ister, but does not chang state

IRQ /FT igna as b cl ed

s l h een ear .

The IRQ /FT pin can also be activated in ked mode. The the battery-bac IRQ /FT goes low if an alarm

ABE and AE are set. Th he power-up transition,

ted during power-up se can be read after system power-up

ine if an alarm was generated d sequence. Figure 4 illustrates alarm timing

ttery mode and power-up states.

occurs and both e ABE and AE bits are cleared during t

but an alarm genera ts AF. Therefore, the AF bit

to determ uring the power-up

during the backup-ba

Figure 2. CLEARING IRQ WAVEFORMS ACTIVE

Figure 3. CLEARING IRQ WAVEFORMS