Datasheet

DS1558
6 of 18
DATA WRITE MODE
The DS1558 is in the write mode whenever
WE
and
CE
are in their active state. The
referenced to the latter occurring transition of
start of a write is
WE or CE . The addresses must be hel
the cycle.
d valid throughout
CE and WE must return inactive for a minimum of t prior to the initiation of a subsequent
read or write cycle. Data in must be valid t prior to the
WR
DS
end of the write and remain valid for t
DH
afterward. In a typical application, the
OE
signal is high during a write cycle. However,
OE
can be active
ten If provided that care is taken with the data bus to avoid bus con tion. OE is low prior to WE
ress inputs. A low transitioning low, the data bus can become active with read data defined by the add
transition on WE then disables the outputs t
WEZ
after WE goes active.
DATA RETENTION MODE
The 5V device is fully accessible and data can be written and read only when V
CC
i
However, when V
CC
is below the power-fail point V
PF
(point at which write prot
internal clock registers and SRAM are blocked from any access. When V falls below the batter
s greater than V
PF
.
ection occurs), the
CC
y switch
point V
SO
(battery supply level), device power is switched from the V
CC
pin to the backup battery. RTC
inal levels.
s greater than V
PF
.
he device power is
C
t . If V
PF
is greater
CC
drops
V
CC
is returned to
All control, data, and address signals must be powered down when V
CC
is powered down.
558 internal clock
current is less than
g. No external protection components
are required, and none should be used. The DS1558 has two battery pins that operate independently; the
DS1558 selects the higher of the two inputs. If only one battery is used, the battery should be attached to
V
BAT1
, and V
BAT2
should be grounded.
INTERNAL BATTERY MONITOR
The DS1558 constantly monitors the battery voltage of the internal battery. The battery-low flag (BLF)
bit of the flags register (B4 of 7FFF0h) is not writable and should always be a 0 when read. If a 1 is ever
present, both battery inputs are below 1.8V and both the contents of the RTC and RAM are questionable.
POWER-ON RESET
A temperature-compensated comparator circuit monitors the level of V
CC
. When V
CC
falls to the power-
fail trip point, the
operation and SRAM data are m
aintained from the battery until V
CC
is returned to nom
The 3.3V device is fully accessible and data can be written and read only when V
CC
i
When V
CC
falls below V
PF
, access to the device is inhibited. If V
PF
is less than V
SO
, t
switched from V
C
o the internal backup lithium battery when V
CC
drops below V
PF
than V
SO
, the device power is switched from V
CC
to the internal backup lithium battery when V
below V
SO
. RTC operation and SRAM data are maintained from the battery until
nominal levels.
BATTERY LONGIVITY
The battery lifetime is dependent on the RAM battery standby current and the DS1
oscillator current. The total battery current is I
OSC
+ I
CCO
. When V
CC
is above V
PF
, I
BAT
50nA. The DS1558 has an internal circuit to prevent battery chargin
RST signal (open drain) is pulled low. When V
CC
returns to nominal levels, the RST
signal continues to be pulled low for a period of 40ms to 200ms. The power-on reset function is
independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled.