Datasheet

DS1558
5 of 18
Figure 1. BLOCK DIAGRAM
ES
V
CC
Table 1. OPERATING MOD
CE OE WE
DQ0–DQ7 MODE POWER
V
IH
X X High-Z Deselect Standby
V
IL
X V
IL
D
IN
Write Active
V
IL
V
IL
V
IH
D
OUT
Read Active
V
CC
> V
PF
V
IL
V
IH
V
IH
High-Z Read Active
V
SO
< V
CC
< V
PF
X X X High-Z Deselect CMOS Standby
V
CC
< V
SO
< V
PF
X X X High-Z Data Retention Battery Current
DATA READ MODE
The DS1558 is in the read mode whenever CE is low and WE is high. The device architecture allows
gh access to any valid address location. Valid data is available at the DQ pins within t
AA
after
the last address input is stable, provided that
ripple-th
rou
CE
and
OE
access times are satisfied. If
CE
or
OE
access
et, valid data is available at the latter of chip-enable access (t
CEA
) or at output-enable
(t
OEA
). The state of the data input/output pins (DQ) is controlled by
tim
es are not m
access time
CE and OE . If the
ated before t
AA
, the data lines are driven to an intermediate state until t
AA
. If the address
inputs are changed while
outputs are activ
CE and OE remain valid, output data remains valid for output-data hold time
), but then goes indeterminate until the next address acces
s. (tOH
NOTE: ANY U S THE RTC.NUSED UPPER ADDRESS PINS MUST BE CONNECTED TO V
CC
TO PROPERLY ADDRES