Datasheet

DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
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Figure 1. Block Diagram
Table 1. Operating Modes
V
CC
CE OE WE
DQ0–DQ7 MODE POWER
V
IH
X X High-Z Deselect Standby
V
IL
X V
IL
D
IN
Write Active
V
IL
V
IL
V
IH
D
OUT
Read Active
V
CC
> V
PF
V
IL
V
IH
V
IH
High-Z Read Active
V
SO
< V
CC
<V
PF
X X X High-Z Deselect CMOS Standby
V
CC
<V
SO
< V
PF
X X X High-Z Data Retention Battery Current
DATA READ MODE
The DS1556 is in the read mode whenever CE (chip enable) is low and WE (write enable) is high. The
device architecture allows ripple-through access to any valid address location. Valid data will be available
at the DQ pins within t
AA
after the last address input is stable, providing that CE and OE access times are
satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip enable
access (t
CEA
) or at output enable access time (t
OEA
). The state of the data input/output pins (DQ) is
controlled by CE and OE. If the outputs are activated before t
AA
, the data lines are driven to an
intermediate state until t
AA
. If the address inputs are changed while CE and OE remain valid, output data
will remain valid for output data hold time (tOH) but will then go indeterminate until the next address
access.
DATA WRITE MODE
The DS1556 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout the
cycle. CE and WE must return inactive for a minimum of t
WR
prior to the initiation of a subsequent read
or write cycle. Data in must be valid t
DS prior to the end of the write and remain valid for t
DH
afterward. In
Maxim
DS1556