Datasheet

Low-Current, SPI-Compatible
Real-Time Clock
14 Maxim Integrated
DS1347
SCLK
R/W A6 A5 A4 A3 A2 A1
1
DIN
DOUT
ADDRESS/COMMAND BYTE
HIGH IMPEDANCE
DATA BYTE
D7 D6 D5 D4 D3 D2 D1 D0
CS
Figure 2a. Single Read
111111
ADDRESS/COMMAND BYTE*
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2
DATA BYTE 1
DATA BYTE N
HIGH IMPEDANCE
R/W A6
D1 D0
CS
SCLK
DIN
DOUT
*ONLY ONE ADDRESS/COMMAND BYTE IS REQUIRED PER BURST TRANSACTION.
Figure 2b. Burst Read
t
CSS
t
CP
t
CH
t
CL
t
CSW
t
DS
t
DH
t
DO
t
CSZ
SPI MODE 3 READ CYCLE SHOWN
SCLK POLARITY CAN BE NON-INVERTED (SPI MODE 1)
D7 D0
R/W A6 A5 A0
CS
t
CSH
SCLK
DIN
DOUT
Figure 3. SPI Bus Timing Diagram