Datasheet

Figure 1. I
2
C Timing
Figure 2. Power-Up/Down Timing
SCL
NOTE: TIMING IS REFERENCED TO V
IL(MAX)
AND V
IH(MIN)
.
SDA
STOP START REPEATED
START
t
BUF
t
HD:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
HD:STA
t
SP
t
SU:STA
t
HIGH
t
R
t
F
t
LOW
RECOGNIZED DON’T CARE RECOGNIZED
SCL
VALID VALID
SDA
HIGH IMPEDANCE
t
REC
t
VCCR
t
VCCF
V
PF
V
CC
DS1339B Low-Current, I
2
C, Serial Real-Time Clock
For High-ESR Crystals
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